KS8995E Micrel Inc, KS8995E Datasheet

KS8995E

Manufacturer Part Number
KS8995E
Description
Manufacturer
Micrel Inc
Datasheet

Specifications of KS8995E

Number Of Primary Switch Ports
5
Fiber Support
Yes
Integrated Led Drivers
Yes
Phy/transceiver Interface
MII/SNI
Power Supply Type
Analog/Digital
Package Type
PQFP
Data Rate (typ)
10/100Mbps
Vlan Support
Yes
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Pin Count
128
Mounting
Surface Mount
Jtag Support
No
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Not Compliant

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KS8995E
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5 510
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KS8995E
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General Description
The KS8995E contains five 10/100 physical layer transceiv-
ers, five MAC (Media Access Control) units with an integrated
layer 2 switch. The device runs in two modes. The first mode
is a five port integrated switch and the second is as a five port
switch with the fifth port decoupled from the physical port. In
this mode access to the fifth MAC is provided using an MII
(Media Independent Interface).
Useful configurations include a stand alone five port switch as
well as a four port switch with a routing element connected to
the extra MII port. The additional port is also useful for a public
network interfacing.
The KS8995E is designed to reside in an unmanaged design
not requiring processor intervention. This is achieved through
I/O strapping or EEPROM programming at system reset time.
Functional Diagram
August 2003
KS8995E
Micrel, Inc. • 1849 Fortune Drive • San Jose, CA 95131 • USA • tel + 1 (408) 944-0800 • fax + 1 (408) 944-0970 • http://www.micrel.com
Transceiver
Physical
EEPROM
MAC
(1K Entries)
Interface
Look Up
1
1
Engine
Transceiver
Physical
SCL
SDA
MAC
2
2
Management
Queue
FIFO and Flow Control
Transceiver
Physical
MAC
3
3
Management
Transceiver
Buffer
Physical
1
MAC
4
4
On the media side, the KS8995E supports 10BaseT,
100BaseTX and 100BaseFX as specified by the IEEE 802.3
committee.
Physical signal transmission and reception are enhanced
through use of analog circuitry that makes the design more
efficient and allows for lower power consumption and smaller
chip die size.
The major enhancements from the KS8995 to the KS8995E
are support for VLAN, traffic priority queuing, EEPROM
programming for expanded control, MDI/MDI-X auto cross-
over.
Data sheets and support documentation can be found on
Micrel’s web site at www.micrel.com.
5-Port 10/100 Integrated Switch with PHY and Frame Buffer
Transceiver
Physical
MAC
(32Kx32)
5
5
Buffers
SRAM
Programming
Interface
LED
and
MII / SNI
(exclusive)
External
Interface
KS8995E
Rev. 1.10
LED[1][3:0]
LED[2][3:0]
LED[3][3:0]
LED[4][3:0]
LED[5][3:0]
M
N
S
I
I
I
MRXD[3:0]
MRXDV
MCOL
MTXD[3:0]
MTXEN
MTXER
MII_CLK
MRXD[0]
MRXDV
MCOL
MTXD[0]
MTXEN
MII_CLK
KS8995E
Micrel

Related parts for KS8995E

KS8995E Summary of contents

Page 1

... MII port. The additional port is also useful for a public network interfacing. The KS8995E is designed to reside in an unmanaged design not requiring processor intervention. This is achieved through I/O strapping or EEPROM programming at system reset time. ...

Page 2

... Supports MDI/MDI-X auto crossover • Single 2.5V power supply • 700mA (1.75W) including physical transmit drivers • Commercial temperature range +70 C • Available in 128-pin PQFP package KS8995E Ordering Information Part Number Temperature Range KS8995E + Micrel Package 128-Pin PQFP August 2003 ...

Page 3

... Update maximum frame length values. 1.05 4/20/01 Correct timing information. 1.06 5/03/01 Correct I/O definition. 1.07 5/11/01 Add MDI/MDI-X description. 1.08 7/25/01 Update timing information. 1.09 8/09/01 Add appendix D & MII timing. Add 10BaseTX power dissipation. 1.10 8/29/03 Convert to new format. August 2003 3 Micrel KS8995E ...

Page 4

... Half-Duplex Back Pressure ............................................................................................................................................. 19 Broadcast Storm Protection ..................................................................................................................................................... 19 MII Interface Operation .................................................................................................................................................................. 21 SNI Interface (7-wire) Operation ................................................................................................................................................... 22 8995E Improvements ..................................................................................................................................................................... 22 Priority Schemes ..................................................................................................................................................................... 22 Per Port Method ...................................................................................................................................................................... 22 802.1p Method ......................................................................................................................................................................... 22 IPv4 DSCP Method ................................................................................................................................................................. 22 Other Priority Considerations .................................................................................................................................................. 22 VLAN Operations ........................................................................................................................................................................... 23 Other Programmable Features ..................................................................................................................................................... 24 EEPROM Operations ...................................................................................................................................................................... 24 Compatibility with KS8995 ............................................................................................................................................................ 24 KS8995E 4 Micrel August 2003 ...

Page 5

... Station MAC Address Registers (all ports – MAC control frames only) ................................................................................... 29 Absolute Maximum Ratings .......................................................................................................................................................... 30 Operating Ratings .......................................................................................................................................................................... 30 Electrical Characteristics .............................................................................................................................................................. 30 Timing Diagrams ............................................................................................................................................................................ 32 Reference Circuit ........................................................................................................................................................................... 36 4B/5B Coding ............................................................................................................................................................................ 37 MLT Coding ............................................................................................................................................................................ 38 802.1q VLAN and 802.1p Priority Frame ...................................................................................................................................... 39 Selection of Isolation Transformers ............................................................................................................................................. 40 Selection of Reference Crystals ................................................................................................................................................... 40 Package Outline and Dimensions ................................................................................................................................................ 41 August 2003 5 Micrel KS8995E ...

Page 6

... KS8995E System Level Applications The KS8995E can be configured to fit either in a five port 10/ 100 application four port 10/100 network interface with an extra MII / SNI port. This MII / SNI port can be connected to an external processor and used for routing purposes or KS8995E 5-Port ...

Page 7

... Not used - float for normal operation (no connect 2.5V for equalizer I 4 Physical receive signal + (differential Physical receive signal - (differential) 4 Ground for equalizer 5 Ground for equalizer I 5 Physical receive signal + (differential Physical receive signal - (differential 2.5V for equalizer Analog ground 7 Micrel KS8995E ...

Page 8

... VDD-IO 74 GND GND 75 P5EXT 76 P5SNI Note power supply GND = ground I = input O = output I/O = bi-directional KS8995E (Note 1) Port Pin Function Not used - float for normal operation (no connect Physical transmit signal + (differential Physical transmit signal - (differential) 5 Ground for transmit circuitry P 5 2.5V for transmit circuitry ...

Page 9

... LED indicator 0 I/O 5 LED indicator 3 I/O 5 LED indicator 2 I/O 5 LED indicator 1 / I/O 5 LED indicator 2.5V for core digital circuitry Ground for digital circuitry O Connect to crystal I Crystal or clock input P 2.5V for phase locked loop circuitry Ground for phase locked loop circuitry 9 Micrel KS8995E ...

Page 10

... RXM[1] 127 VDD_RX[1] 128 GND_ANA GND Note power supply GND = ground I = input O = output I/O = bi-directional KS8995E (Note 1) Port Pin Function 2 Ground for clock recovery circuitry P 2 2.5V for clock recovery circuitry P 1 2.5V for clock recovery circuitry 1 Ground for clock recovery circuitry I Factory test pin – ...

Page 11

... KS8995E I/O Grouping Group Name Description PHY Physical Interface MII Media Independant Interface SNI Serial Network Interface IND LED Indicators UP Unmanaged Programmable CTRL Control and Miscellaneous TEST Test (Factory) PWR/GND Power and Ground August 2003 11 Micrel KS8995E ...

Page 12

... LED[1:5][1] L LED[1:5][2] L LED[1:5][3] L KS8995E Description Differential inputs (receive) for connection to media (transformer or fiber module) Differential outputs (transmit) for connection to media (transformer or fiber module) Fiber signal detect - connect to fiber signal detect output on fiber module. Tie low for 100TX mode. ...

Page 13

... Programs no excessive collision drop at reset time Drop after 16 collisions F drop after 16 collisions Programs a limit for broadcast frames at reset time limit limit of broadcast frames Note: EEPROM programming can limit broadcast frames at 25%, 12 3%. “EEPROM Register” See 7 bits 7-6. 13 Micrel KS8995E ...

Page 14

... All unmanaged programming takes place at reset time only. For unmanaged programming Float Pull-down Pull-up. “Reference Circuits” See section. KS8995E (Note 1) Description Programs force 100BaseTX / 10BaseT mode at reset time. Disable auto-negotiation to use this force mode. Use the table below to set this mode on the appropriate port. ...

Page 15

... Ground for clock recovery. 2.5V for phase locked loop circuitry. Ground for phase locked loop circuitry. Analog ground. 2.5V for analog circuits. Analog ground. 2.5V for core digital circuitry. 2.5V or 3.3V for MII interface. Ground for digital circuitry. 15 Micrel KS8995E ...

Page 16

... LED[5][0] VDD GND X2 X1 VDD_PLL GND_PLL GND_RCV[2] VDD_RCV[2] VDD_RCV[1] GND_RCV[1] MUX[2] MUX[1] FXSD[1] AOUT GND_RX[1] RXP[1] RXM[1] VDD_RX[1] GND_ANA 1 KS8995E 128-Pin PQFP (PQ) 16 Micrel 65 MTXD[0] MTXD[1] MTXD[2] MTXD[3] MTXEN GND VDD SDA SCL TEST[2] TEST[1] VDD_RCV[3] GND_RCV[3] GND_RCV[4] VDD_RCV[4] VDD_RCV[5] GND_RCV[5] ...

Page 17

... RXP or RXM input from falsely triggering the decoder. When the input exceeds the squelch limit, the PLL locks onto the incoming signal and the KS8995E decodes a data frame. The receiver clock is maintained active during idle periods in between data reception. August 2003 ...

Page 18

... The KS8995E will turn off everything except for the Energy Detect and PLL circuits when the cable is not installed on an individual port basis. In other words, the KS8995E will shutdown most of the internal circuits to save power if there is no link. MDI/MDI-X Auto Crossover The KS8995E supports MDI/MDI-X auto crossover ...

Page 19

... If the DA look-up results is a “match”, the KS8995E will use the destination port information to determine where the packet goes. • If the DA look-up result is a “miss”, the KS8995E will forward the packet to all other ports except the port that received the packet. ...

Page 20

... KS8995E will issue a flow control frame (XOFF), containing the maximum pause time defined in IEEE standard 802.3x. Once the resource is freed up, the KS8995E will send out the other flow control frame (XON) with zero pause time to turn off the flow control (turn on transmission to the port). A hysterisis feature is provided to prevent flow control mechanism from being activated and deactivated too many times ...

Page 21

... For half-duplex operation there is a signal that indicate a collision has occurred during transmission. Note that the signal MRXER is not provided on the MII interface for the KS8995E. Normally this would indicate a receive error coming from the physical layer device, but since this port connects to a MAC device it is not appropriate. If the connecting device has a MRXER pin, this should be tied low on the other device ...

Page 22

... Priority Schemes The KS8995E can determine priority through three different means. The first method is a simple per port method, the second is via the 802.1p frame tag and the third is by viewing the DSCP (TOS) field in the IPv4 header. Of course for the priority to be effective, the high and low priority queues must be enabled on the destination port or egress point ...

Page 23

... VLAN Enforcement: Allows unicast frames to adhere or ignore the VLAN configuration VLAN Mask Registers: Allows configuration of individual VLAN grouping. Note reserved bit in each of the registers (sliding position). VLAN Tag Insertion Values: Specifies the VLAN tag to be inserted if enabled (see above) Table 4. VLAN Control 23 Micrel “EEPROM Memory Map” section. KS8995E ...

Page 24

... The EEPROM interface utilizes 2 pins that provide a clock and a serial data path. As part of the initialization sequence, the KS8995E reads the contents of the EEPROM and loads the values into the appropriate registers. Note that the first two bytes in the EEPROM must be “55” and “95” respectively for the loading to occur properly. If these first two values are not correct, all other data will be ignored ...

Page 25

... Ports 1 and 2 are trunked, ports 3 and 4 are trunked 11 = Ports are trunked TOS priority classification enable for port Enable Disable 802.1p priority classification enable for port Enable Disable Port based priority classification for port Enable Disable 25 Micrel Default (chip) Value 0x55 0x95 KS8995E ...

Page 26

... Control Register KS8995E Description Insert VLAN tags for port 2 if non-existent 1 = Enable Disable Strip VLAN tags for port 2 if existent 1 = Enable Disable Enable high and low output priority queues for port Enable Disable Priority buffer reserve for high priority traffic ...

Page 27

... Port 1 not in the same VLAN as port 2 Reserved Port 5 inclusion 1 = Port 5 in the same VLAN as port Port 5 not in the same VLAN as port 3 Port 4 inclusion 1 = Port 4 in the same VLAN as port Port 4 not in the same VLAN as port 3 Reserved 27 Micrel Default (chip) Value 000 000 000 KS8995E ...

Page 28

... Port 2 VLAN Tag Insertion Value Registers 15 7 3-0 16 7-0 KS8995E Description Port 2 inclusion 1 = Port 2 in the same VLAN as port Port 2 not in the same VLAN as port 3 Port 1 inclusion 1 = Port 1 in the same VLAN as port Port 1 not in the same VLAN as port 3 Reserved Port 5 inclusion ...

Page 29

... MAC address [39:32] MAC address [31:24] MAC address [23:16] MAC address [15:8] MAC address [7:0] 29 Micrel Default (chip) Value 000 0 0x0 0x00 000 0 0x0 0x00 000 0 0x0 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x40 0x05 0x43 0x5E 0xFE KS8995E ...

Page 30

... The device is not guaranteed to function outside its operating rating. Unused inputs must always be tied to an appropriate logic voltage level (Ground Note (heat spreader) in package. Note 4. Specification for packaged product only. KS8995E Operating Ratings (Note 1) Supply Voltage (V Ambient Temperature (T Package Thermal Resistance (Note 3) PQFP (Note 4) ...

Page 31

... KS8995E Symbol Parameter 10BaseTX Transmit (measured differentially after 1:1 transformer) V Peak Differential Output Voltage P Jitters Added Rise/Fall Time August 2003 Condition 50 from each output from each output Micrel Min Typ Max Units 2 KS8995E ...

Page 32

... Clock Cycle CYC t Set-Up Time S t Hold Time H Symbol Parameter t Clock Cycle CYC t Output Valid OV KS8995E Figure 2. EEPROM Input Timing Table 6. EEPROM Input Timing Parameters Figure 3. EEPROM Output Timing Table 7. EEPROM Output Timing Parameters 32 Micrel Min Typ Max Units 12288 Min ...

Page 33

... Clock Cycle CYC t Output Valid OV August 2003 Figure 4. SNI (7-Wire) Input Timing Table 8. SNI (7-Wire) Input Timing Parameters Figure 5. SNI (7-Wire) Output Timing Table 9. SNI (7-Wire) Output Timing Parameters 33 Micrel Min Typ Max Units 100 Min Typ Max Units 100 KS8995E ...

Page 34

... KS8995E Figure 6. Reverse MII Timing–Receive Data from MII Symbol Parameter t Clock Cycle CYC t Set-Up Time S t Hold Time H Table 10. Reverse MII Timing–Receive Data from MII Parameters KS8995E (100BaseT) (10BaseT) 34 Micrel Min Typ Max Units 40 ns 400 August 2003 ...

Page 35

... KS8995E Figure 7. Reverse MII Timing–Transmit Data to MII Symbol Parameter t Clock Cycle CYC t Output Valid OV Table 11. Reverse MII Timing–Transmit Data to MII Parameters August 2003 (100BaseT) (10BaseT) 35 Micrel Min Typ Max Units 40 ns 400 KS8995E ...

Page 36

... V 220 Pull-Up 10k LED pin KS8995E 2.5 V 220 Float LED pin KS8995E 2.5 V Pull Down 220 Pull-down LED pin KS8995E 1k Figure 8. Unmanaged Programming Circuit Transformer Only Quad Single HB826-2 HB726-1 H1164 H1102 558-5999-Q9 S558-5999-U7 PH406466 PT163020 Table 12. Magnetic Vendor List 36 Micrel Integrated RJ4 & ...

Page 37

... Data value E Data value F Idle Start delimiter part 1 Start delimiter part 2 End delimiter part 1 End delimiter part 2 Transmit error Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Micrel KS8995E ...

Page 38

... ESD 1 Idle Variable KS8995E instance if the MLT3 level is at its lowest point the next two NRZI transitions will change the MLT3 signal initially to the middle level followed by the highest level (second NRZI transition). On the next NRZI change, the MLT3 level will decrease to the middle level ...

Page 39

... KS8995E 802.1q VLAN and 802.1p Priority Frame The 3-bit of 802.1p priority is embedded into the 802.1q VLAN frame as described below: August 2003 Figure 10. 802.1q and 802.1p Frame Format 39 Micrel KS8995E ...

Page 40

... ISET resistor value. Selection of Reference Crystal An oscillator or crystal with the following typical characteristics is recommended. Characteristics Name Frequency Frequency Tolerance (max.) Jitter (max.) KS8995E (Note 1) Value Test Condition 350 H 100mV, 100KHz, 8mA ...

Page 41

... Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify August 2003 128-Pin PQFP (PQ (408) 944-0970 FAX WEB Micrel for any damages resulting from such use or sale. © 2003 Micrel, Incorporated. 41 http://www.micrel.com Micrel KS8995E ...

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