SLXT332QE.G2 Cortina Systems Inc, SLXT332QE.G2 Datasheet
SLXT332QE.G2
Specifications of SLXT332QE.G2
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SLXT332QE.G2 Summary of contents
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... Meets or exceeds industry specifications including ITU G.703, ANSI T1.403, AT&T Pub 62411 and ITU-T G.742 Compatible with most industry standard framers ® LXT332 Dual T1/E1 ® LXT332 Dual T1/E1 Line Interface Unit with Crystal-less Jitter Computer to PBX interface (CPI & DMI) ...
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LXT332 Datasheet 249075, Revision 2.0 26 June 2007 *Other names and brands may be claimed as the property of others. ® Cortina Systems LXT332 Dual T1/E1 Line Interface Unit with Crystal-less Jitter Attenuation © Cortina Systems, Inc. 2007 Legal Disclaimer ...
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LXT332 Datasheet 249075, Revision 2.0 26 June 2007 Contents 1.0 Block Diagram ............................................................................................................................... 6 2.0 Overview......................................................................................................................................... 7 2.1 Standard LXT332 Features .................................................................................................. 7 2.1.1 Tri-state Outputs ...................................................................................................... 7 2.1.2 Bipolar or Unipolar Data I/O..................................................................................... 7 2.1.3 B8ZS or HDB3 Zero ...
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LXT332 Datasheet 249075, Revision 2.0 26 June 2007 7.0 Mechanical Specifications .......................................................................................................... 43 Figures 1 Block Diagram ................................................................................................................................. 6 2 Pin Assignments (Frame Graphic) and Package Markings (PLCC) ................................................ 9 3 Pin Assignments (Frame Graphic) and Package Markings (QFP Package) ...
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LXT332 Datasheet 249075, Revision 2.0 26 June 2007 Revision History First release of this document from Cortina Systems, Inc. Initial release. ® Cortina Systems LXT332 Dual T1/E1 Line Interface Unit with Crystal-less Jitter Attenuation Revision 2.0 Revision Date: 26 June ...
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LXT332 Datasheet 249075, Revision 2.0 26 June 2007 1.0 Block Diagram Figure 1 Block Diagram QRSS / BPV Generator TCLK B8ZS/HDB3 TPOS Unipolar TNEG Encoder Encoder Enable Remote Decoder Loopback Loopback RLOOP Enable Enable Jitter JASEL Attenuator B8ZS/HDB3 RPOS Unipolar ...
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... Dual Loopback Dual Loopback (DLOOP) enables simultaneous loopbacks to both the framer and the line. The TCLK, TPOS and TNEG framer inputs are routed through the jitter attenuator and looped back to the RCLK, RPOS and RNEG outputs. The RTIP/RRING line inputs are looped back through the timing recovery block and line driver onto the TTIP/TRING outputs ...
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LXT332 Datasheet 249075, Revision 2.0 26 June 2007 2.2.3 Built In Self Test (QRSS) - The LXT332 can generate and transmit a Quasi Random Signal Source (QRSS) pattern to Built-In Self Test (BIST) applications. Logic errors and bipolar violations can ...
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LXT332 Datasheet 249075, Revision 2.0 26 June 2007 3.0 Pin Assignments and Signal Descriptions Figure 2 and Figure 3 respectively. Note that many pins have two functions. The active function is determined by the particular mode of operation selected. functions, ...
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LXT332 Datasheet 249075, Revision 2.0 26 June 2007 Figure 3 Pin Assignments and Package Markings (QFP Package RCLK0 2 TAOS0 / SCLK 3 LEN20 / VCQ0 4 LEN10 ...
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... PLCC Tristate Output Enable. When held High, forces all output pins to high When held Low, Bipolar I/O mode is selected. In this mode, the framer interface is bipolar (TPOS/TNEG and RPOS/RNEG), and the B8ZS/HDB3 encoders are disabled. When clocked by MCLK, Unipolar I/O mode is selected. In this mode, the framer ...
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LXT332 Datasheet 249075, Revision 2.0 26 June 2007 Table 1 Host Mode and Bipolar Host Mode Pin Descriptions (Sheet Pin Pin 1 Symbol I/O QFP PLCC Transmit Tip and Ring 8 14 TTIP0 AO drive a 35 ...
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LXT332 Datasheet 249075, Revision 2.0 26 June 2007 Table 1 Host Mode and Bipolar Host Mode Pin Descriptions (Sheet Pin Pin 1 Symbol I/O QFP PLCC Violation Insert, High Frequency Clock, or QRSS 29 35 VCQ1 DI/O ...
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... PLCC Tristate Output Enable. When held High, forces all output pins to high When held Low, Bipolar I/O mode is selected. In this mode, the framer interface is bipolar (TPOS/TNEG and RPOS/RNEG), and the B8ZS/HDB3 encoders are disabled. When clocked by MCLK, Unipolar I/O mode is selected. In this mode, the framer ...
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... Driver Failure Monitor. This signal goes High to indicate a driver output short in one DFM DO both ports. Remote Loopback Enable framer) are ignored and the data received from the twisted 13 19 RLOOP0 DI onto the line at the RCLK frequency. Note that if LLOOP is High, Remote Loopback is inhibited (on the respective port). ...
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LXT332 Datasheet 249075, Revision 2.0 26 June 2007 Table 3 Hardware Mode and Bipolar Hardware Mode Pin Descriptions Pin Pin Symbol I/O 2 QFP PLCC Receive Clock 33 39 RCLK1 DO input signal. Under Loss of Signal (LOS) conditions, RCLK1 ...
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... The integrated crystal-less jitter attenuator may be positioned in either the transmit or receive path, or disabled. Each DLIU transceiver back-end interfaces with a framer through either bipolar or unipolar data I/O channels. The DLIU may be controlled by a microprocessor through the serial port (Host mode hard-wired pins for stand-alone operation (Hardware mode). ...
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... The two transmitters in the LXT332 are identical. The following paragraphs describe the operation of a single transmitter. Transmit data from the framer is clocked serially into the device at TPOS/TNEG in the bipolar mode or at TDATA in the unipolar mode. The transmit clock (TCLK) supplies the input synchronization ...
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LXT332 Datasheet 249075, Revision 2.0 26 June 2007 4.2.2 Pulse Shape The transmitted pulse shape is determined by Line Length equalizer control signals LEN0 through LEN2 as shown in Host mode the LEN codes are input through the serial interface. ...
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LXT332 Datasheet 249075, Revision 2.0 26 June 2007 4.4 Jitter Attenuation A digital Jitter Attenuation Loop (JAL) combined with an Elastic Store (ES) provides jitter attenuation. The JAL is internal and requires no external crystal nor high-frequency (higher than line ...
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LXT332 Datasheet 249075, Revision 2.0 26 June 2007 The Clock Edge (CLKE) signal determines when the SDO and receive data outputs are valid, relative to the Serial Clock (SCLK) or RCLK as listed in Specifications section for SIO timing. 4.7.1 ...
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LXT332 Datasheet 249075, Revision 2.0 26 June 2007 Table 7 SIO Input Bit Settings (See Figure 5) Mode Remote Loopback Local Loopback Dual loopback Transmit all ones Reset Table 8 Serial Data Output Bit Coding (See Figure 6) Bit D5 ...
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LXT332 Datasheet 249075, Revision 2.0 26 June 2007 Figure 5 SIO Write Operation PS SCLK ADDRESS COMMAND BYTE R SDI SDO: remains high impedance ADDRESS / COMMAND R/W A0 BYTE CLEAR / ...
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LXT332 Datasheet 249075, Revision 2.0 26 June 2007 Figure 7 Interrupt Handling Start Interrupts Enabled Interrupts INT* = High Does an No (No Interrupt) Interrupt Condition INT* = Low (Interrupt) Read Output Status Word* Read Output Status Word* (bits D5 ...
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LXT332 Datasheet 249075, Revision 2.0 26 June 2007 4.7.3 Interrupt Handling The Host mode provides two latched Interrupt output pins, INT0 and INT1, one for each LIU port. An interrupt is triggered by a change in the LOS or DFM ...
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LXT332 Datasheet 249075, Revision 2.0 26 June 2007 Figure 8 TAOS Data Path 4.9.2 Local Loopback Local Loopback (LLOOP) is selected when LLOOP = 1 and RLOOP = 0. In LLOOP mode, the receiver circuits are inhibited. The transmit clock ...
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LXT332 Datasheet 249075, Revision 2.0 26 June 2007 Figure 10 Local Loopback - Selectable JA TPOS TNEG TCLK RCLK RNEG RPOS 4.9.3 Remote Loopback Remote Loopback (RLOOP) is selected when RLOOP = 1 and LLOOP = 0. Note that TAOS ...
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LXT332 Datasheet 249075, Revision 2.0 26 June 2007 Figure 11 Remote Loopback TPOS TNEG TCLK RCLK RNEG RPOS TPOS TNEG TCLK RCLK RNEG RPOS 4.9.4 Dual Loopback Dual Loopback (DLOOP) is selected when RLOOP = 1, LLOOP = 1 and ...
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LXT332 Datasheet 249075, Revision 2.0 26 June 2007 4.9.5 QRSS Built-In Self Test - Host Mode The QRSS Built -In Self Test (BIST) is available only under Host control. As shown in Figure 13, the QRSS BIST function is selected ...
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LXT332 Datasheet 249075, Revision 2.0 26 June 2007 The transceiver can be reset from either the Host or Hardware mode. In Host mode, reset is commanded by writing 1s to RLOOP and LLOOP, and TAOS (bits D5, ...
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... I/O mode. Driving JASEL Low switches the jitter attenuation circuits into the transmit paths for both LIU ports. Figure 14 shows a pair of framers (a dual framer could also be used). A Clock Adapter (CLAD) converts the 2.048 MHz backplane clock to provide the 1.544 MHz input to the MCLK and TCLK inputs of both LIU ports. ...
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LXT332 Datasheet 249075, Revision 2.0 26 June 2007 Table 9 Recommended Transformer Values Parameter Turns Ratio (T1) Turns Ratio (E1) Primary Inductance Leakage Inductance Interwinding Capacitance DC Resistance (Pri.) ET (Breakdown Voltage) Table 10 Transformer Combinations Xfmr LEN 1 Ratio ...
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LXT332 Datasheet 249075, Revision 2.0 26 June 2007 Figure 14 Typical T1 Application (Host Control Mode, Bipolar I/O) Clock Adapter CLKI 2.048 MHz 1.544 MHz CLKO MCLK TCLK TCLK0 TPOS0 TPOS0 TNEG0 TNEG0 RPOS0 RPOS0 RNEG0 RNEG0 RCLK0 RCLK0 TPOS1 ...
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LXT332 Datasheet 249075, Revision 2.0 26 June 2007 5.5 2.048 Mbps E1/CEPT Interface Applications 5.5.1 E1 Coaxial Applications shows the line interface for a typical 2.048 Mbps E1 coaxial (75 Ω) application. Figure 15 The LEN code should be set ...
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LXT332 Datasheet 249075, Revision 2.0 26 June 2007 Figure 16 Typical E1 120 W Application (Hardware Control Mode) 2.048 MHz Clock Source MCLK TCLK TCLK0 TPOS0 TPOS0 TNEG0 TNEG0 RPOS0 RPOS0 RNEG0 RNEG0 RCLK0 RCLK0 TPOS1 TPOS1 TNEG1 TNEG1 TCLK1 ...
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LXT332 Datasheet 249075, Revision 2.0 26 June 2007 6.0 Test Specifications Note: Information in Table 11 performance specifications of the LXT332 Dual Line Interface Unit and are guaranteed by test, except as noted, by design. Table 11 Absolute Maximum Ratings ...
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LXT332 Datasheet 249075, Revision 2.0 26 June 2007 Table 13 Electrical Characteristics (Over Recommended Operating Conditions) (Sheet Parameter Sym 4 Input leakage current Ill - 2 Three state leakage current Isl 5 Input pull down current (MCLK) ...
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LXT332 Datasheet 249075, Revision 2.0 26 June 2007 Table 14 Analog Specifications (Over Recommended Operating Conditions) (Sheet Parameter 10 Hz Input jitter tolerance 750 Hz 10 kHz – 100 kHz Allowable consecutive zeros before LOS T1 Jitter ...
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LXT332 Datasheet 249075, Revision 2.0 26 June 2007 Figure 17 Serial Data Input Timing Diagram SCLK CDH SDI LSB CONTROL BYTE Figure 18 Serial Data Output Timing Diagram PS SCLK t CDV ...
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LXT332 Datasheet 249075, Revision 2.0 26 June 2007 Figure 20 Transmit Clock Timing TCLK TPOS TNEG Table 16 Receive Timing Characteristics (See Figure 19) Parameter - DSX 1 Receive clock period E1 Receive clock duty cycle - DSX 1 Receive ...
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LXT332 Datasheet 249075, Revision 2.0 26 June 2007 Figure 21 Typical Receiver Input Jitter Tolerance (Loop Mode) 1000 UI 100 4.9 Hz AT&T 62411, Dec 1990 (T1 1 ...
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LXT332 Datasheet 249075, Revision 2.0 26 June 2007 Figure 22 Typical Jitter Transfer Performance E1 Jitter 10 Transfer Performance -10 dB -20 dB -30 dB - Jitter Transfer Performance 0 dB ...
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LXT332 Datasheet 249075, Revision 2.0 26 June 2007 7.0 Mechanical Specifications Figure 23 PLCC Package Specifications ® Cortina Systems LXT332 Dual T1/E1 Line Interface Unit with Crystal-less Jitter Attenuation Plastic ...
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LXT332 Datasheet 249075, Revision 2.0 26 June 2007 Figure 24 QFP Package Specifications Quad Flat Pack Dim ...
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