TXC-03401BITQ Transwitch Corporation, TXC-03401BITQ Datasheet

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TXC-03401BITQ

Manufacturer Part Number
TXC-03401BITQ
Description
Manufacturer
Transwitch Corporation
Datasheet

Specifications of TXC-03401BITQ

Number Of Transceivers
1
Operating Supply Voltage (typ)
5V
Screening Level
Industrial
Mounting
Surface Mount
Package Type
TQFP
Operating Supply Voltage (min)
4.75V
Operating Supply Voltage (max)
5.25V
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Lead Free Status / RoHS Status
Not Compliant
FEATURES
• DS3 payload access, bit-serial or nibble-parallel
• C-bit parity or M13 operating mode
• C-bit interface (13 C-bits in, 14 out)
• Detect and generate DS3 AIS, and idle signals
• Transmit reference generator for serial operation
• Transmit and receive Far End Alarm and Control
• Maskable hardware interrupt for eight alarms
• Transmit single errors: framing, FEBE, C-bit parity,
• FEBE, C-bit, and P-bit performance counters
• Counters for F-bit and M-bit errors
• Counter for coding violations and excessive zeros
• Transmit-to-Receive and Receive-to-Transmit
• Outputs can be set to high-impedance state
• Selectable mode for TXC-03401 emulation
• Single +5 volt power supply
• Available as 68-pin plastic leaded chip carrier or
Copyright
TranSwitch and TXC and are registered trademarks of TranSwitch Corporation
(FEAC) with double word capability and automatic
transmission
and P-bit parity
loopbacks
80-pin thin plastic quad flat package (TQFP)
LINE SIDE
DS3 NRZ I/O
clock & data
2001 TranSwitch Corporation
TranSwitch Corporation
Tel: 203-929-8810
+5V
Microprocessor
interface
3 Enterprise Drive
DS3 stuff bits
clock & data
TXC-03401B
DS3 Framer
Fax: 203-926-9453
DS3F
Transmit errors
DESCRIPTION
APPLICATIONS
The DS3F is designed for DS3 framer applications in
which broadband payloads are mapped into the 44.736
Mbit/s DS3 frame format. Although the C-bit parity for-
mat is recommended, the DS3F can also operate in the
M13 mode. In the C-bit parity format, the DS3F provides
a separate interface for selected C-bits. The DS3F also
provides for transmitting and receiving the FEAC chan-
nel and Blue code AIS conditions, and generates and
detects DS3 AIS, DS3 idle, P-bit parity and C-bit parity.
In addition, performance counters are provided, as well
as the ability to generate single framing, FEBE, C-bit
parity and P-bit parity errors. The device also provides
X-bit inversion, receive loop timing and indications for
FEAC idle channel, FEAC word stack overflow and
Severely Errored Frame. The payload interface is select-
able through software as either a bit-serial or nibble-par-
allel format.
• Subrate multiplexing
• Wideband data or video transport
• DS3 monitor and test
• Channel extenders
• DS3 test sets
Shelton, Connecticut 06484
clocks & data
C-bits I/O
www.transwitch.com
Serial/nibble
clock, data &
frame output
Serial/nibble
clock, data &
frame input
Transmit DS3
reference generator
output
TERMINAL SIDE
DS3F Device
DATA SHEET
TXC-03401B
Document Number:
DS3 Framer
USA
TXC-03401B-MB
Ed. 6, June 2001

Related parts for TXC-03401BITQ

TXC-03401BITQ Summary of contents

Page 1

... DS3 NRZ I/O clock & data Microprocessor interface Copyright 2001 TranSwitch Corporation TranSwitch and TXC and are registered trademarks of TranSwitch Corporation TranSwitch Corporation Tel: 203-929-8810 DESCRIPTION The DS3F is designed for DS3 framer applications in which broadband payloads are mapped into the 44.736 Mbit/s DS3 frame format ...

Page 2

... Microprocessor Read Cycle ..................................................................................................30 17 Microprocessor Write Cycle ...................................................................................................31 18 Power Supply Connections ...................................................................................................32 19 DS3F TXC-03401B 68-Pin Plastic Leaded Chip Carrier .......................................................45 20 DS3F TXC-03401B 80-Pin Thin Profile Plastic Quad Flat Package ......................................46 DATA SHEET LIST OF FIGURES - DS3F TXC-03401B Page Page TXC-03401B-MB Ed. 6, June 2001 ...

Page 3

... P I/O ALE SEL OENA FORCEOE CXD CXCK CXF CXDCC DS3 D3TD Send D3TC FORCECP/CVCNT FORCEPP/EXZCNT FORCEFEBE Figure 1. DS3F TXC-03401B Block Diagram DATA SHEET TERMINAL SIDE Receive DS3 Interpreter Output Transmit Frame Reference Generator RT Payload Loopback Input Transmit Note: N.C. indicates No Connection. ...

Page 4

... The DS3F receives a line side DS3 data signal (D3RD) and a clock signal (D3RC) from a line interface device such as the TranSwitch ART/ARTE VLSI device (TXC-02020/02021) or DS3LIM-SN module (TXC-20153D or TXC-20153G). The DS3 Frame Alignment Block performs DS3 frame alignment that will not lock to a false framing pattern. There are internal 8-bit F- and M-bit error counters included in the Extended-features mode of the framer to monitor errors ...

Page 5

... Indications of these events are provided to the DS3F by TranSwitch's ART or ARTE devices (TXC-02020/02021). The ART's CV output pin indicates both coding violations and excessive zeros. Therefore, only the CVCNT input pin to the DS3F is required to count both types of event. When the ARTE is used in con- junction with the DS3F, there are separate CV and EXZ inputs available to the DS3F, which can be or-gated together in the DS3F's 16-bit counter, if required ...

Page 6

... WR STUFD/HINT 15 STUFC 16 17 VDD 18 AD7 AD6 19 AD5 20 AD4 21 22 GND AD3 23 AD2 24 AD1 25 26 AD0 Please see Figure 19 for package dimensions. Figure 2. DS3F TXC-03401B 68-Pin PLCC Pin Diagram DATA SHEET DS3F 53 TXC-03401B 52 68-Pin PLCC 51 (Top View DS3F TXC-03401B XNIB0 XNIB1 ...

Page 7

... RCG 7 GND 8 SPARE 9 TXC-03401B RCS/RCN 10 CRF 11 80-Pin TQFP CRCK 12 CRD 13 VDD 14 RNIB3 15 SPARE 16 RNIB2 17 18 RNIB1 RDS/RNIB0 Please see Figure 20 for package dimensions. Figure 3. DS3F TXC-03401B 80-Pin TQFP Pin Diagram DATA SHEET DS3F (Top View DS3F TXC-03401B OENA SEL TEST GND ...

Page 8

... DS3 data sig- nal. Data (D3TD) is clocked out on rising edges of the clock. O CMOS DS3 Transmit Data: DS3 line side serial transmit 4mA data DS3F TXC-03401B Name/Function 5% Name/Function Name/Function TXC-03401B-MB Ed. 6, June 2001 ...

Page 9

... SER and RGCEN are both set CMOS Receive Clock Gap Signal: The active low gap 4mA signal is synchronous with each overhead bit in the serial DS3 frame (first bit in the 85-bit group DS3F TXC-03401B Name/Function TXC-03401B-MB Ed. 6, June 2001 ...

Page 10

... DS3F. In order to meet cross- connect objectives, the clock must operate at 44.736 Mbit/s with a stability of 20 ppm and a duty cycle of (50 10)%. If XCK fails, the DS3F uses the D3RC receive clock in its place DS3F TXC-03401B Name/Function TXC-03401B-MB Ed. 6, June 2001 ...

Page 11

... An active low, one clock cycle wide (TCOUT) pulse that is synchronous with bit 1 in the DS3 frame. May be used as the serial data transmit framing pulse (XFSI) if properly delayed such that XFSI is aligned with an overhead-bit clock cycle DS3F TXC-03401B Name/Function Name/Function TXC-03401B-MB Ed. 6, June 2001 ...

Page 12

... C-Bit Receive Data: Serial interface for receiving 4mA the following C-bits in the C-bit parity mode: C2, C3, C4, C5, C6, C13, C14, C15, C16, C17, C18, C19, C20, and C21. Availability of data is indicated by the clock signals CRDCC and CRCK, described above DS3F TXC-03401B Name/Function Name/Function TXC-03401B-MB Ed. 6, June 2001 ...

Page 13

... The indication is active until the next X1 state is detected. O TTL DS3 Received X-Bit 2: An output indication of the 4mA state of the second X-bit received in the DS3 frame (bit 680). The indication is active until the next X2 state is detected DS3F TXC-03401B Name/Function Name/Function TXC-03401B-MB Ed. 6, June 2001 ...

Page 14

... I TTLp Force DS3 Overhead Bit Error: An active low signal used in conjunction with the overhead enable signal (OENA) for introducing an overhead bit error in the next transmitted 85-bit group DS3F TXC-03401B Name/Function TXC-03401B-MB Ed. 6, June 2001 ...

Page 15

... CVEXZ at Addresses 12H and 13H, is incremented when the pin is high during the rising edge of D3RC. This pin is intended to be driven by the CV Coding Violation / Excessive Zeros output pin of the TranSwitch TXC-02020 ART device or the CV Coding Violation output pin of the TranSwitch TXC-02021 ARTE device. I ...

Page 16

... The DS3F memory I/O is selected by placing a low on the select pin. I/O TTL Address/Data Bus: These pins constitute the time 8mA multiplexed address and data bus for accessing the registers which reside in the DS3F memory map DS3F TXC-03401B Name/Function TXC-03401B-MB Ed. 6, June 2001 ...

Page 17

... DS3F TXC-03401B Unit Conditions V Note 1 V Note Note ft/min linear airflow Level per EIA/JEDEC JESD22-A112-A % Note 2 % non-condensing V Note 3 Unit Test Conditions o C/W 0 ft/min linear airflow o C/W 0 ft/min linear airflow Unit Test Conditions Inputs switching TXC-03401B-MB Ed. 6, June 2001 ...

Page 18

... DD 4.75 <V < 5. 5.25 DD Test Conditions 4.75 <V < 5.25 DD 4.75 <V < 5. 5.25; Input = 0 volts DD Test Conditions 4.75 <V < 5.25 DD 4.75 <V < 5. 5.25 DD Test Conditions V = 4.75 -2 4.75 4 LOAD LOAD Test Conditions V = 4.75 -4 4.75 4 TXC-03401B-MB Ed. 6, June 2001 ...

Page 19

... FALL DATA SHEET Type Max Unit 4.0 mA -4.0 mA 1.9 ns 2.0 ns Type Max Unit 0.4 V 8.0 mA -4.0 mA 1 DS3F TXC-03401B Test Conditions LOAD LOAD Test Conditions 4.75 <V < 5.25 DD 4.75 <V < 4.75 -4 4.75 8 LOAD LOAD TXC-03401B-MB Ed. 6, June 2001 ...

Page 20

... PWH PWL t SU(1) t H(1) t SU(2) t H(2) t SU(3) t H(3) Symbol Min t 20 CYC t 8.0 PWH t 8.0 PWL -- 40 t 4.0 SU(1) t 6.0 H(1) t 4.0 SU(2) t 6.0 H(2) t 4.0 SU(3) t 6.0 H( DS3F TXC-03401B + V )/2 for output signals Type Max Unit 22. TXC-03401B-MB Ed. 6, June 2001 ...

Page 21

... PWH t 8.0 PWL t 3 CYC t t PWL PWH t OD(1) Nibble Nibble #1175 # 1176 t OD( Symbol Min t 89 CYC t 40 PWH t 40 PWL t 20 OD( OD( DS3F TXC-03401B t PWH Type Max Unit 22. Nibble # 1 Type Max Unit 90.5 111 CYC TXC-03401B-MB Ed. 6, June 2001 ...

Page 22

... Note: XNIB data input is latched at the midpoint of XNC low. DATA SHEET t CYC t t PWL PWH t H( Symbol Min t 89.0 CYC t 40 PWH t 40 PWL t 26 SU(1) t -14 H( DS3F TXC-03401B N3 N4 Type Max Unit 90.5 111 2.0 8.0 ns TXC-03401B-MB Ed. 6, June 2001 ...

Page 23

... RCS low time RDS, RCG, RFS output delay after RCS or RNIB3 DATA SHEET One DS3 Frame CYC t t PWL PWH t OD Symbol Min t 20 CYC t 8.0 PWH t 8.0 PWL t 0 DS3F TXC-03401B BIT 4760 Type Max Unit 22. 2.5 5.0 ns TXC-03401B-MB Ed. 6, June 2001 ...

Page 24

... DATA SHEET One DS3 Frame t CYC t t PWH PWL XCK t SU(1) t H(1) XDS t SU(2) t H(2) XFSI Symbol Min t 20 CYC t 8.0 PWH t 8.0 PWL t 0.0 SU(1) t 7.0 H(1) t 2.0 SU(2) t 5.0 H( DS3F TXC-03401B BIT 4760 Type Max Unit 22. TXC-03401B-MB Ed. 6, June 2001 ...

Page 25

... D3TC clock period (see Figure 5). CYC DATA SHEET Figure 10. C-Bit Transmit Input Timing C5 C6 C13 C14 C15 t CYC(1) Symbol Min t CYC( DS3F TXC-03401B C16 C17 C18 C19 C20 C21 Type Max Unit 170 CYC ns ns 170 CYC CYC TXC-03401B-MB Ed. 6, June 2001 ...

Page 26

... CRF pulse width (high) Note the RCS clock period (see Figure 8). CYC DATA SHEET C13 C14 C15 t CYC(1) Symbol Min t CYC(1) t OD(1) t 5.0 OD( DS3F TXC-03401B C16 C17 C18 C19 C20 C21 Type Max Unit 170 CYC 170 CYC CYC TXC-03401B-MB Ed. 6, June 2001 ...

Page 27

... Type t 20 22.3 CYC( 0 PWH(1) CYC( 0 PWL(1) CYC( 22.3 CYC(2) CYC( 0 PWH(2) PWH(1) CYC(1) t 2.0 4.0 OD(1) t 2.0 4.0 OD(2) t 2.0 4.0 OD(3) t 2.0 4.0 OD(4) t 2.0 4.0 OD( DS3F TXC-03401B t OD(2) Max Unit 7 7 TXC-03401B-MB Ed. 6, June 2001 ...

Page 28

... Note: FORCEOE resets OENA. DATA SHEET PWL Symbol Min Type PWL PW(1) t OD(2) t PW(2) Symbol Min Type t 20 22.35 CYC t 0.0 OD( PW(1) CYC PW(2) CYC t 0.0 OD( DS3F TXC-03401B Max Unit Note Max Unit ns 7 CYC CYC CYC TXC-03401B-MB Ed. 6, June 2001 ...

Page 29

... The clock output STUFC is intended to be used to strobe the data output STUFD low frequency signal that repeats at 15.2 s intervals. STUFD has a 3.8 s set up time to STUFC and a hold time of 11.4 s after STUFC . DATA SHEET t CYC Symbol Min t CYC DS3F TXC-03401B Stuff bit, subframe 2 Type Max Unit 22.35 ns 3800 ns TXC-03401B-MB Ed. 6, June 2001 ...

Page 30

... DATA SHEET Figure 16. Microprocessor Read Cycle t SU(1) H(1) t H(2) Address t W(2) t OD( W(4) Symbol Min t 30 PW(1) t 0.0 W( SU( H( OD(1) t OD( W(3) t 100 PW( W( TXC-03401B t W(1) t OD(1) Data t w(3) PW(2) Type Max Unit TXC-03401B-MB Ed. 6, June 2001 DS3F ...

Page 31

... A minimum of 10 clock cycles must occur after power-up, before the write cycles are valid. DATA SHEET Figure 17. Microprocessor Write Cycle t H(1) t W(2) t PW(2) t W(4) Symbol Min t 50 PW(1) t 0.0 W( SU( H( SU( H( PW( W( DS3F TXC-03401B t W( SU(2) H(2) Data t W(3) Type Max Unit TXC-03401B-MB Ed. 6, June 2001 ...

Page 32

... DATA SHEET 4/1 VDD GND 17/14 VDD GND 27/30 VDD GND 38/44 VDD GND 51/54 VDD GND 63/70 VDD GND DS3F TXC-03401B Figure 18. Power Supply Connections - DS3F TXC-03401B + NOTE: All capacitors are 0.1 microfarads unless otherwise specified. TXC-03401B-MB Ed. 6, June 2001 ...

Page 33

... DS3F TXC-03401B Bit 2 Bit 1 Bit 0 TXLOC XRX2 XRX1 SER 3LOOP XTX LOC X2ERR X1ERR ITX1 RESET LPTIME Unused** Unused** STKOVFL C21 MCB1 CPARINV HINTEN MOOFW CRDCINV RFEAC3 RFEAC2 RFEAC1 RTLOC SEF XERR XERREN EXZEN CVEN TXC-03401B-MB Ed. 6, June 2001 ...

Page 34

... D3RC receive clock cycles. D3RC clock must be present to count XCK cycles. A failure causes the receive clock to become the transmit clock. This permits the micropro- cessor interface and transmitter to continue to function. Recovery occurs on the first transition of XCK DS3F TXC-03401B TXC-03401B-MB Ed. 6, June 2001 ...

Page 35

... Transmit data is provided at the output (D3TD). 0 XTX Transmit X-Bits: The X-bits may be used to transmit a yellow alarm low-speed signaling channel. A one written into this bit position causes the DS3F to transmit a one for both X1 and X2. DATA SHEET Description - DS3F TXC-03401B TXC-03401B-MB Ed. 6, June 2001 ...

Page 36

... DS3 frame count in conjunction with the count contained in the framing bit error counter (Address 02H) to deter- mine an approximate bit error rate (BER). In the M13 mode, the counter is frozen during a DS3 loss of signal or an out of frame condition. DATA SHEET Description - DS3F TXC-03401B TXC-03401B-MB Ed. 6, June 2001 ...

Page 37

... For example, to activate or deactivate a loopback, the first loopback control code word must be trans- mitted 10 times, followed by 10 repetitions of the second DS3 (or DS1) line code word. (See also DFEXEC at Address 0DH, bit 6.) DATA SHEET Description - DS3F TXC-03401B TXC-03401B-MB Ed. 6, June 2001 ...

Page 38

... FEAC channel busy - No message received since last read cycle 1 0 FEAC channel idle - No message received since last read cycle 0 1 New message received - FEAC channel busy 1 1 New message received - FEAC channel idle - DS3F TXC-03401B 06H Status TXC-03401B-MB Ed. 6, June 2001 ...

Page 39

... Transmit Reference Generator does not switch to the DS3 receive clock, the LPTIME bit is invalid for serial mode applications. If the DS3 receive clock fails in this mode, the DS3F switches over to the transmit clock. DATA SHEET Description - DS3F TXC-03401B TXC-03401B-MB Ed. 6, June 2001 ...

Page 40

... The XFSI input pulse must not be applied while RTPLOOP is set TESTLOCK Test Lock: Test bit to reset the transmit frame counter at a different time with respect to the receive. For test purposes only. Normally set to 0. DATA SHEET Description - DS3F TXC-03401B TXC-03401B-MB Ed. 6, June 2001 ...

Page 41

... This field is used for the XXXXXX content of the first word of a double word message. Both FEAC words are sent ten times automatically when DFEXEC is set to 1. DATA SHEET Description - DS3F TXC-03401B TXC-03401B-MB Ed. 6, June 2001 ...

Page 42

... FEAC words. If more than four FEAC words have been received since the last read of this register then the STKOVFL bit (Address 09H, bit 0) will be set to 1. The stack will retain the 4 most recent FEAC words. DATA SHEET Description - DS3F TXC-03401B TXC-03401B-MB Ed. 6, June 2001 ...

Page 43

... RXOOFEN put pin (pin 15/67) when the corresponding latched alarm bit is set RXAISEN the register at Address 10H, provided that the HINTEN bit at Address 0EH, bit 2 is set RXIDLEN 3 NFEACIEN 2 RTLOCEN 1 SEFEN 0 XERREN DATA SHEET Description - DS3F TXC-03401B TXC-03401B-MB Ed. 6, June 2001 ...

Page 44

... The FORCECP input pin is then defined as the CVCNT (coding violation) input pin and the FORCEPP input pin as the EXZCNT (excessive zeros) input pin to the CVEXZ 16-bit counter in the registers at Addresses 12H and 13H. DATA SHEET Description - DS3F TXC-03401B TXC-03401B-MB Ed. 6, June 2001 ...

Page 45

... Figure 19 80-pin Thin Profile Plastic Quad Flat Package suitable for surface mounting, as shown in Figure 20. 0.990 SQ. 0.954 SQ. 0.075 0.800 SQ TRANSWITCH TXC-03401BIPL 26 27 TOP VIEW Note: All dimensions are shown in inches and are nominal unless otherwise indicated. Figure 19. DS3F TXC-03401B 68-Pin Plastic Leaded Chip Carrier DATA SHEET 0.200 MAX. 0.020 MIN BOTTOM VIEW ...

Page 46

... Proprietary TranSwitch Corporation Information for use Solely by its Customers The DS3F device is also available as an 80-pin Thin Profile Plastic Quad Flat Package suitable for surface mounting, as illustrated in Figure 20 (the PLCC version is shown in Figure 19 TRANSWITCH 12.00 9.50 Typ 14.00 TXC-03401BITQ 80 1 INDEX PIN #1 SEE DETAIL “A” Figure 20 ...

Page 47

... ORDERING INFORMATION Part Number: TXC-03401BIPL Part Number: TXC-03401BITQ RELATED PRODUCTS TXC-02020 (02021), ART (ARTE) VLSI Device (Advanced DS3/STS-1 Receiver/Transmitter). Performs the receive and transmit line interface functions required for transmission of DS3 (44.736 Mbit/s) or STS-1 (51.840 Mbit/s) signals across a coaxial interface. The ARTE is an extended-feature version of the ART larger package ...

Page 48

... Fax: (650) 949-6705 Web: www.atmforum.com Tel: 2 761 66 77 Fax: 2 761 66 79 Tel: 3 3438 3694 Fax: 3 3438 3698 Tel: (800) 854-7179 (within U.S.A.) Tel: (314) 726-0444 (outside U.S.A.) Fax: (314) 726-6418 Web: www.global.ihs.com Tel Fax Web: www.etsi.org - DS3F TXC-03401B TXC-03401B-MB Ed. 6, June 2001 ...

Page 49

... Tel: (800) 433-5177 (within U.S.A.) Tel: (503) 693-6232 (outside U.S.A.) Fax: (503) 693-8344 Web: www.pcisig.com Tel: (800) 521-CORE (within U.S.A.) Tel: (908) 699-5800 (outside U.S.A.) Fax: (908) 336-2559 Web: www.telcordia.com Tel: 3 3432 1551 Fax: 3 3432 1553 Web: www.ttc.or. DS3F TXC-03401B TXC-03401B-MB Ed. 6, June 2001 ...

Page 50

... Proprietary TranSwitch Corporation Information for use Solely by its Customers LIST OF DATA SHEET CHANGES This change list identifies those areas within this updated DS3F Data Sheet that have significant differences relative to the previous and now superseded DS3F TXC-03401B Data Sheet: Updated DS3F Data Sheet: Previous DS3F Data Sheet: The page numbers indicated below of this updated Data Sheet include changes relative to the previous Data Sheet ...

Page 51

... TranSwitch covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. DATA SHEET - NOTES - - DS3F TXC-03401B TXC-03401B-MB Ed. 6, June 2001 ...

Page 52

... TranSwitch Corporation 3 Enterprise Drive • • Shelton, CT 06484 USA Tel: 203-929-8810 - • • Fax: 203-926-9453 www.transwitch.com ...

Page 53

... Product Information Sheets, Data Sheets, Application Notes, Technical Bulletins and other publications are sent to you. You may also choose to provide the same information by fax (203.926.9453 e-mail (info@txc.com telephone (203.929.8810). Most of these documents will also be made immediately available for direct download as Adobe PDF files from the TranSwitch World Wide Web Site (www ...

Page 54

... Please complete the registration form on this back cover sheet, and fax or mail it, if you wish to receive updated documentation on this TranSwitch product as it becomes available. • TranSwitch Corporation 3 Enterprise Drive (Fold back on this line second, then tape closed, stamp and mail.) TranSwitch Corporation Attention: Marketing Communications Dept. 3 Enterprise Drive Shelton, CT 06484-4694 U.S.A. • ...

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