TXC-06880BIOG

Manufacturer Part NumberTXC-06880BIOG
ManufacturerTranswitch Corporation
TXC-06880BIOG datasheet
 


Specifications of TXC-06880BIOG

Operating Supply Voltage (typ)1.8/3.3VOperating Temperature ClassificationIndustrial
MountingSurface MountLead Free Status / RoHS StatusNot Compliant
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PRELIMINARY
FEATURES
2 Configurable Media Access Controllers (MACs)
Each MAC is configurable as 8 Fast Ethernet ports (10/100 Mbit/s), 2 Fast Ethernet
ports with extended buffers or 1 Gigabit Ethernet port (10/100/1000 Mbit/s)
SPI-3 interface configurable in Link or PHY layer mode, operating at 125 MHz
Support for Jumbo frames (9600 Bytes) and Super Jumbo frames (12000 Bytes)
Full and Half Duplex (CSMA/CD) operation (Half Duplex only supported for Fast
Ethernet)
Programmable SPI-3 burst size from 64 to 1024 bytes
Frame integrity verification (FCS and Frame length checks) and generation
Packet statistics and Performance monitoring support for RMON per port
PAUSE frame flow control for Full Duplex mode
“Raise Carrier” flow control for Half Duplex mode
Programmable high and low FIFO watermarks for flow control trigger
Automatic PAUSE frame generation and termination
Filtering of PAUSE frames in Ethernet Ingress or Egress
Port aggregation from Ethernet to SPI-3, using routing tag encapsulation
8/16 bit Microprocessor interface, selectable between Intel or Motorola
JTAG Boundary Scan (IEEE 1149.1 Standard)
580-lead Plastic Ball Grid Array (PBGA) package, 27 mm x 27 mm
APPLICATIONS
Metro Edge Routers and Switches
Ethernet over SONET/SDH Multi-Service Provisioning Platforms (MSPPs)
IP DSLAMs
3G Wireless Base Stations
3G Radio Network Controllers (RNCs)
Multi-Service Access Platforms (MSAPs)
TranSwitch Corporation
Tel: 203-929-8810
Envoy-CE2 Device
8/16 bit @ 33/66 MHz
Network Side
Host Interface
Envoy-CE2
Ethernet
SPI-3 to
(SMII/MII/GMII)
Ethernet Controller
16 10/100
2 10/100/1000
TXC-06880
MMII
3 Enterprise Drive
Shelton, Connecticut 06484
Fax: 203-926-9453
www.transwitch.com
TM
SPI-3 to Ethernet Controller
TXC-06880
DATA SHEET
TXC-06880-MB, Ed. 4
February 2005
Switch Side
SPI-3
8/16/32 bit
@ 104/125 MHz
JTAG
USA

TXC-06880BIOG Summary of contents

  • Page 1

    ... Ethernet SPI-3 to (SMII/MII/GMII) Ethernet Controller 16 10/100 2 10/100/1000 TXC-06880 MMII • 3 Enterprise Drive • Shelton, Connecticut 06484 • Fax: 203-926-9453 • www.transwitch.com TM SPI-3 to Ethernet Controller TXC-06880 DATA SHEET TXC-06880-MB, Ed. 4 February 2005 Switch Side SPI-3 8/16/32 bit @ 104/125 MHz JTAG • USA ...

  • Page 2

    ... Applications Engineering for current information on this product. U.S. Patents No. 4,967,405; 5,040,170; 5,142,529; 5,265,096; 5,331,641; 5,724,362; 6,577,651B1 U.S. and/or foreign patents issued or pending Copyright 2005 TranSwitch Corporation Envoy is a trademark of TranSwitch Corporation TranSwitch, TXC and PHAST are registered trademarks of TranSwitch Corporation IMPORTANT NOTICE - PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 ...

  • Page 3

    ... Receive MAC Data Flow....................................................................................................... 59 6.1.2 Receive MAC Checks ........................................................................................................... 59 6.1.2.1 6.1.2.2 6.1.2.3 6.1.2.4 6.1.2.5 6.1.3 Receive MAC Statistics ........................................................................................................ 60 6.1.3.1 PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 T ABLE OF PHY Mode ................................................................................................................... 17 Link Mode .................................................................................................................... 18 Boundary Scan Operation ........................................................................................... 20 Boundary Scan Reset.................................................................................................. 20 Boundary Scan Schematic .......................................................................................... 21 Boundary Scan Chain.................................................................................................. 21 FCS Check: ................................................................................................................. 59 Frame Length Check: ...

  • Page 4

    ... Pad Short Ethernet Frames Option:............................................................................ 67 Frame Length Check:.................................................................................................. 67 Maximum Frame Size Check: ..................................................................................... 67 Back to Back Interframe Gap Option: ......................................................................... 67 Source Address Replace Option:................................................................................ 67 PAUSE Frame Filter Option: ....................................................................................... 67 Preamble Length Option: ............................................................................................ 67 Counters:..................................................................................................................... 68 Automatic PAUSE Frame Generation......................................................................... 72 Host Initiated PAUSE Frame Generation.................................................................... 72 PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 ...

  • Page 5

    ... SMII Sync In/Out Timing ............................................................................................................. 44 12. SMII Transmit Interface Timing ................................................................................................... 45 13. SMII Receive Interface Timing .................................................................................................... 45 14. GMII Transmit Interface Timing Using GmTXCLKI ..................................................................... 46 15. GMII/MII Receive Interface Timing Using GmRXCLK ................................................................. 47 16. MII Transmit Interface Timing Using GmMTXCLK ...................................................................... 48 17. Management MII Interface Timing............................................................................................... 49 18. ...

  • Page 6

    ... Summary of the Change Table of Contents and List of Figures. ‘List of Data Sheet Changes’ section. Section 2.1.1. Section 2.1.9. Figure 18. Section 6.2.1.1 and added Section “2014” HEET HANGES Figure 17. Figure 23. Figure 24. 6.2.1.2. and “2040”. Changed “STPA PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 ...

  • Page 7

    ... Modified Description for Bit Range 7-0 of Address “200C”, 101 Modified Bit Range 15-8 Description for Address “4008”. 106 Modified Bit 107 Modified Bit “24”, “25”, PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 Summary of the Change Table of Contents and List of Figures. ...

  • Page 8

    ... Fast Ethernet and Gigabit Ethernet PHY/SerDes devices via the SMII and GMII. The Envoy-CE2 incorporates on-chip buffering to promote high performance without congestion or loss of data and provides backpressure support on both the Ethernet and SPI-3 interfaces Overview - - 1.0 O PRELIMINARY TXC-06880-MB, Ed. 4 VERVIEW February 2005 ...

  • Page 9

    ... GE Jumper Setting Jumper settings sets the correct value on the I/O card connector lead for configuring the Envoy-CE2 Ethernet interface Figure 1. Flexible Architecture for Ethernet Over SONET/SDH & Router Application PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 - Overview - Router Blade NPU Envoy-CE2 Common Connector having all the GMII & SMII Signals plus configuration leads to configure the Ethernet interface of the Envoy-CE2 ...

  • Page 10

    ... Figure 2. Functional Block Diagram of the Envoy-CE2 Functional Description - - 2.0 F UNCTIONAL Channel n Channel 0 CHn EGRESS FIFO CONTROLLER Apply Backpressure FLOW CONTROL Detect Backpressure CHn INGRESS FIFO CONTROLLER D ESCRIPTION ISPID(31:0) U CH0 X ISPISTPA ISPIPTPA 8/16/32 OSPISTPA Bit OSPIPTPA SPI CH0 D OSPID(31: PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 ...

  • Page 11

    ... KByte ingress FIFO per Configurable MAC • 32 KByte egress FIFO per Configurable MAC • Far end switch side loopback for diagnostic capability • Packet statistics and performance monitoring support for Remote Network Monitoring (RMON) PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 - Functional Description - OR OR ...

  • Page 12

    ... The following sequence needs to be performed when switching from GMII mode to MII mode and vice versa: • Enable Soft Reset for the MAC (Register 0x4000 Bit 31 for Port 0) • Reprogram Interface Mode Register (Register 0x4004 Bits 8-9) • Remove Soft Reset Functional Description - - PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 ...

  • Page 13

    ... Note: Series termination resistor values are dependent on the selection of the Ethernet PHY. Please consult the specification of the Ethernet PHY for series termination resistor values Figure 3. GMII (1000 Mbit/s) Only Interface Connection PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 - Functional Description - SMII Reference Clock is needed for ...

  • Page 14

    ... RX[0-3](A,B) RX[4-7](A,B) G(A,B)RXDV G(A,B)RXER G(A,B)COL G(A,B)CRS G(A,B)MTXCLK 125 MHz Reference Clock TxData[0-3] TxData[4-7] GMII 125 MHz TxClk TxEnable TxError RxClk (2.5/25/125 MHz) RxData[0-3] RxData[4-7] RxDataValid RxError Collision (Half Duplex Only) Carrier (CRS) (Half Duplex Only) MII 2.5/25 MHz Clock ...

  • Page 15

    ... When Scan mode and Auto PHY address increment are enabled, the range of addresses scanned will be between “PHY Address” (Register 0x0048 Bits 8-12) and PHY number 31. 2. Envoy’s Management Media Independent Interface (MMII Master mode. PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 - Functional Description - ...

  • Page 16

    ... SPI-3 address. Individual SPI-3 port addresses are calculated by adding the (base address x 32) to the logical Ethernet port number. For example, the SPI-3 address of port 11 with a base address of 3 will give a SPI-3 port address of (11 + (3x32)) =107 Functional Description - - PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 ...

  • Page 17

    ... Packet data may be transferred across the Receive Interface in chunks, programmable from 8 to 2040 bytes byte increments. In the Receive direction (SPI-3 output), the time between consecutive transfers (pause) is programmable cycles. Figure 7. Envoy-CE2 in PHY Layer Mode PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 - Functional Description - TFCLK TENB ...

  • Page 18

    ... OSPIMOD[1:0 ] STPA OSPISTPA PTPA OSPIPTPA TADR[7:0] OSPITADR[7:0] RFCLK ISPICLK RENB ISPIRENB RDAT[31:0] ISPID[31:0] RPRTY ISPIPRTY RVAL ISPIRVAL RSOP ISPISOP REOP ISPIEOP RERR ISPIERR RSX ISPIRSX RMOD[1:0] ISPIMOD[1:0] ISPITENB ISPISTPA ISPIPTPA ISPITADR[7:0] ISPITSX OSPIRENB OSPIRVAL OSPIRSX Envoy-CE2 PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 ...

  • Page 19

    ... The boundary scan test bus interface consists of four input signals and an output signal. The four input signals are Test Clock (TCK), Test Mode Select (TMS), Test Data Input (TDI) and PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 - Functional Description - ...

  • Page 20

    ... V Input, Output and Input/Output Parameters section of this Data Sheet for worst case leakage currents of all devices sharing this pull-down resistor Functional Description - - Figure Figure 9. requirements listed in the IL PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 ...

  • Page 21

    ... Boundary Scan Schematic 2.1.9.4 Boundary Scan Chain A Boundary Scan Description Language (BSDL) source file for the Envoy-CE2 is available via the Products page of the TranSwitch Internet World Wide Web site at www.transwitch.com. PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 - Functional Description - Boundary Scan Register ...

  • Page 22

    ... This is the bottom view. The leads are solder balls. See 2. Power supply leads are shown as solid black circles and ground leads are shown as cross- hatched circles. Figure 10. Envoy-CE2 Lead Diagram Technical Characteristics - - 3.0 T ECHNICAL BOTTOM VIEW HARACTERISTICS Figure 25 for package information. PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 ...

  • Page 23

    ... Vt=500mV~600mV). This prevents from turning on the parasitic diode between power rails, avoiding latch up. The external diode will be turned off when V its normal voltage. *Note Input Output Power Tristate PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 - Technical Characteristics - I/O/P * ...

  • Page 24

    ... T14, T15, T16, T17, T18, T23, T24, U9, U10, U11, U12, U13, U14, U15, U16, U17, U18, U24, V9, V10, V11, V12, V13, V14, V15, V16, V17, V18, V24, V25, V26, W25, Y26 Technical Characteristics - - I/O/P * Name/Function P VSS: Ground 0 (zero) volts reference. PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 ...

  • Page 25

    ... C22 TMS B23 TDI E21 TCK D22 PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 - Technical Characteristics - I/O Connect: NC leads are not to be connected, not even to another NC lead, but must be left floating. Connection of NC leads may impair performance or cause damage to the device. Some NC leads may be assigned functions in future upgrades of the device ...

  • Page 26

    ... CMOS Transfer Acknowledge: Active low signal indicating 24 mA normal completion of the bus transfer. This output requires an external pull-up resistor. Note: Device asserts this high before tri-stating to improve acknowledge timing. Name/Function . Active low to enable device test. Name/Function PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 ...

  • Page 27

    ... UPD2 D8 UPD1 C7 UPD0 B6 WRDS B5 RDWR C6 IRQ B15 PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 - Technical Characteristics - I/O/P* Type I LVTTL Microprocessor Address Bus: 15-bit address bus used by the Host Processor for accessing the Envoy-CE2 for a read/write cycle. UPA14 is the Most Significant Bit (MSB). I/O ...

  • Page 28

    ... Transmit Data Port 3: SMII port 3 data out signal. 12mA I LVTTL Receive Data Port 3: SMII port 3 data in signal. O CMOS Transmit Data Port 4: SMII port 4 data out signal. 12mA I LVTTL Receive Data Port 4: SMII port 4 data in signal. Name/Function Name/Function PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 ...

  • Page 29

    ... RX1B T1 TX2B T2 RX2B T3 TX3B U1 RX3B T4 TX4B U2 RX4B U3 PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 - Technical Characteristics - I/O/P* Type O CMOS Transmit Data Port 5: SMII port 5 data out signal. 12mA I LVTTL Receive Data Port 5: SMII port 5 data in signal. O CMOS Transmit Data Port 6: SMII port 6 data out signal ...

  • Page 30

    ... Transmit Data Port 0A: Bit 0 (LSB) of 8-bit GMII A 12mA Transmit Interface in GMII mode or Bit 0 of 4-bit MII A Transmit interface. I LVTTL Receive Data Port 0A: Bit 0 (LSB) of 8-bit GMII A Receive Interface in GMII mode or Bit 0 of 4-bit MII A Receive interface. Name/Function Name/Function PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 ...

  • Page 31

    ... GMII A (MII Mode) Carrier Sense: This active high input signal is the carrier sense lead used in MII mode for the GMII A interface. I LVTTL GMII A (MII Mode) TXCLK: This is the TXCLK signal used in MII mode for the GMII A interface. Envoy-CE2 Device DATA SHEET TXC-06880 ...

  • Page 32

    ... Transmit Data Port 2B: Bit 2 of 8-bit GMII B Transmit 12mA Interface in GMII mode or Bit 2 of 4-bit MII B Transmit interface. I LVTTL Receive Data Port 2B: Bit 2 of 8-bit GMII B Receive Interface in GMII mode or Bit 2 of 4-bit MII B Receive interface. Name/Function PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 ...

  • Page 33

    ... LVTTL GMII B (MII Mode) Carrier Sense: This active high input signal is the carrier sense lead used in MII mode for the GMII B interface. I LVTTL GMII B (MII Mode) TXCLK: This is the TXCLK signal used in MII mode for the GMII B interface. I/O/P* Type O CMOS ...

  • Page 34

    ... SPI-3 Mode: ISPID(31-0); ISPID31 is MSB. I LVTTL SPI-3 Input Bus Parity: This input signal indicates the parity calculated over the ISPID(31-0) bus, when start of transfer or read (Link layer mode)/write (PHY layer mode) enable signals are asserted. Name/Function PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 ...

  • Page 35

    ... ISPITADR2 AB11 ISPITADR1 AF9 ISPITADR0 AC10 ISPISTPA AC12 ISPIPTPA AF11 PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 - Technical Characteristics - I/O/P* Type I LVTTL SPI-3 Input Data Word Modulo: These 2 inputs indicate the number of valid data bytes in ISPID(31- 0). The ISPIMOD bus should always be all zero, except during the last double-word transfer of a frame on ISPID(31-0) ...

  • Page 36

    ... MHz for SPI-3 emulation. CMOS SPI-3 Output Data Bus: 32-bit bus used to transmit 12mA data to the Link Layer device. 8-bit SPI-3 Mode: OSPID(7-0); OSPID7 is MSB. 16-bit SPI-3 Mode: OSPID(15-0); OSPID15 is MSB. 32-bit SPI-3 Mode: OSPID(31-0); OSPID31 is MSB. Name/Function Name/Function PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 ...

  • Page 37

    ... AE23 OSPITADR3 AD22 OSPITADR2 AC21 OSPITADR1 AB20 OSPITADR0 AF23 PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 - Technical Characteristics - Type CMOS SPI-3 Output Bus Parity: This output signal indicates 12mA the parity calculated over OSPID(31-0) bus. CMOS SPI-3 Output Data Word Modulo: These 2 inputs 12mA indicate the number of valid data bytes in OSPID(31-0) ...

  • Page 38

    ... SPI-3 in Master mode I LVTTL SPI-3 Data Bus Width: SPI-3 Data Bus Width select 32-bit mode 01 - 16-bit mode 10 - 8-bit mode 11 - Reserved I LVTTL Configuration for CMACA (Configurable MAC A) Ports Ethernet interface mode select 00 - OFF GMII/MII Extended SMII SMII Name/Function Name/Function PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 ...

  • Page 39

    ... Symbol Lead No. I/O/P* CFGCMACB1 A21 CFGCMACB0 B20 CFGUPMD A18 PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 - Technical Characteristics - Type I LVTTL Configuration for CMACB (Configurable MAC B) Ports 8 to 15: Ethernet interface mode select 00 - OFF GMII/MII Extended SMII SMII I LVTTL Configuration Pin for selecting Host processor ...

  • Page 40

    ... DD1.8 V -0.3 3.9 DD3.3 V -0.5 5 -55 150 Level 100 % ESD absolute value 2000 LU V ALUES Conditions V Notes Notes Note 5 C Note ft/min. linear airflow Per IPC/JEDEC J-STD-020B Note 2 Non-condensing V Note 3 Meets JEDEC STD-78 PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 ...

  • Page 41

    ... Parameter Input leakage current Input capacitance 4.4.2 Input Parameters For LVTTLpu (internal pull-up resistor) Parameter Input current Input leakage current Input capacitance PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 - Selected Parameter Values - Min Typ Max - 15.6 - Min Typ Max 3.3 3.45 100 105 ...

  • Page 42

    ... Min Typ Max 2.0 0.8 - 2.4 0.4 8.0 -8.0 Unit Test Conditions Unit Test Conditions - Unit Test Conditions - Unit Test Conditions V 3.14 < V < 3.46 DD33 V 3.14 < V < 3.46 DD33 3.46 DD33 3.14 DD33 3.14 DD33 PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 ...

  • Page 43

    ... Input/Output Parameters For LVTTL/CMOS 16mA Parameter Input leakage current Input capacitance PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 - Selected Parameter Values - Min Typ Max 2.0 0.8 - 2.4 0.4 16.0 -16.0 Envoy-CE2 Device DATA SHEET TXC-06880 Unit Test Conditions V 3.14 < V < 3.46 DD33 V 3.14 < ...

  • Page 44

    ... SSYNCIN (Input) SSYNCOUTn (Output Parameter SMIIREFCLKn period SMIIREFCLKn duty cycle SSYNCIN setup time to SMIIREFCLKn SSYNCIN hold time from SMIIREFCLKn SSYNCOUTn delay from SMIIREFCLKn Timing Characteristics - - 5.0 T IMING Symbol Min 1 1 HARACTERISTICS t D Typ Max Unit PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 ...

  • Page 45

    ... TXmn (Output) Note Load on All Outputs Parameter TX delay from SMIIREFCLKn mn Figure 13. SMII Receive Interface Timing SMIIREFCLKn (Input (Input) Parameter RX setup to SMIIREFCLKn mn RX hold from SMIIREFCLKn PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 - Timing Characteristics - Symbol Min t 1 Symbol Min t 1 Envoy-CE2 Device ...

  • Page 46

    ... Envoy-CE2 Device DATA SHEET TXC-06880 Figure 14. GMII Transmit Interface Timing Using GmTXCLKI GmTXCLKI (Input) GmTXCLKO (Output) GmTXEN (Output) TXmn (Output) GmTXER (Output) Note load on GMII outputs Parameter GmTXCLKI duty cycle GmTXCLKI PERIOD GmTXCLKO duty cycle GmTXCLKO period GmTXCLKO (low to high transition time, ...

  • Page 47

    ... GmRXCLK GmRXDV, RXmn, GmRXER setup to GmRXCLK Note: The GMII and MII Receive Interface Timing diagrams are specified together in since they are the same. The GMII and MII Transmit Interface Timing diagrams are specified separately in PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 - Timing Characteristics - ...

  • Page 48

    ... Envoy-CE2 Device DATA SHEET TXC-06880 Figure 16. MII Transmit Interface Timing Using GmMTXCLK GmMTXCLK (Input) GmTXEN (Output) TXmn (Output) GmTXER (Output) Note load on GMII outputs Parameter GmMTXCLK duty cycle GmMTXCLK PERIOD GmMTXCLK (low to high transition time, 10% to 90%) GmTXEN, TXmn, GmTXER delay from ...

  • Page 49

    ... Figure 17. Management MII Interface Timing MDC (Output) MDIO (In/Out) Note load on all MII outputs Parameter MDC frequency MDC duty cycle MDIO delay from MDC MDIO setup to MDC MDIO hold from MDC PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 - Timing Characteristics - Symbol Min 1/t 1 ...

  • Page 50

    ... TSPITENB, ISPID(31-0), PRTY, SOP, EOP, MOD(1-0), ERR, TSX, ADR(7-0) hold from ISPICLK STPA, PTPA(7-0) delay from ISPICLK Timing Characteristics - - Please refer to OIF SPI-3 specification for protocol waveform. Symbol 1/t Min Typ Max Unit 25 125 MHz PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 ...

  • Page 51

    ... OSPIRVAL (Output) OSPIRSX (Output) Note load on SPI-3 interface outputs. Parameter OSPICLK frequency OSPICLK duty cycle OSPIRENB setup to OSPICLK OSPIRENB hold from OSPICLK OSPID(31-0), PRTY, MOD(1-0), ERR, SOP, EOP, VAL, RSX delay from OSPICLK PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 - Timing Characteristics - ...

  • Page 52

    ... TMS hold time after TCK TDI setup time before TCK TDI hold time after TCK TDO delay after TCK Timing Characteristics - - t H(1) t SU( Symbol Min Typ 2.0 SU(1) t 3.0 H(1) t 1.0 SU(2) t 5.0 H( Max Unit 23.0 ns PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 ...

  • Page 53

    ... Setup time of UPA to rising edge UPCLK Setup time of RDWR to rising edge UPCLK Setup time rising edge UPCLK Setup time of falling edge WRDS to rising edge UPCLK Setup time of UPD to rising edge UPCLK Hold time of UPA to rising edge UPCLK PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 - Timing Characteristics - SU5 ...

  • Page 54

    ... Only applies if a write access is followed by a read access. RDWR may stay low between 2 successive write accesses to the same peripheral. g. Timing is relative to the rising edge before the one during which DTACK is asserted Timing Characteristics - - Symbol Min Typ Max Unit - 15.0 ns 7 Cycles PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 ...

  • Page 55

    ... Setup time of UPA to rising edge UPCLK Setup time of RDWR to rising edge UPCLK Setup time rising edge UPCLK Setup time of falling edge WRDS to rising edge UPCLK Hold time of UPA to rising edge UPCLK Hold time of RDWR to rising edge UPCLK PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 - Timing Characteristics - ...

  • Page 56

    ... Timing is relative to the rising edge before the one during which DTACK is asserted Timing Characteristics - - Symbol Min 15.0 SU6 d t 3.0 H6 Typ Max Unit - 20.0 ns 7 Cycles - ns 12.0 ns PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 ...

  • Page 57

    ... Assertion time for WRDS (Write Strobe) Write completion to DTACK going low UPD, UPA, CS hold time to DTACK going low CS inactive hold time after write completion (for back to back writes or reads) Note: The microprocessor clock must be present for correct operation. PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 - Timing Characteristics - ...

  • Page 58

    ... UPD, UPA, CS hold time to DTACK going low CS inactive hold time after read completion (for back to back reads or writes) Note: The microprocessor clock must be present for correct operation Timing Characteristics - - Symbol Min in Max in UPCLK UPCLK Cycles Cycles PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 ...

  • Page 59

    ... SPI port. When the IFIFO is configured for Streaming mode, a bad FCS is appended to the frame. 6.1.2.3 Maximum Frame Size Check: The maximum size of the accepted Ethernet frame is programmable. The default value is 1536 (decimal) bytes. Frames exceeding the programmed maximum frame size are PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 - Operation - 6.0 O Envoy-CE2 Device ...

  • Page 60

    ... Count of Control frames received with unknown opcode (32 bit) • Count of frames received with a valid FCS and length less than 64 bytes (32 bit) • Count of frames received with a valid FCS and total byte count is between 1519 and Operation - - PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 ...

  • Page 61

    ... Frame data stored in the Ingress FIFO will be made available for transfer on the SPI-3 interface, depending on two selectable modes of operation: • Store and Forward Mode: When a complete frame has been written into the Ingress PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 - Operation - 71. If the Ethernet device transmitting frames, ignores the backpressure “ ...

  • Page 62

    ... Frame format at SPI-3 Output Interface Destination Address Source Address (6 bytes) (6 bytes Operation - - Destination Source Length/Type Address Address (2 bytes) (6 bytes) (6 bytes) Length/Type Data (2 bytes) (46 to 1500 bytes) Data Frame Check (46 to 1500 Sequence bytes) (4 bytes) Frame Check Sequence (4 bytes) PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 ...

  • Page 63

    ... PHY’s Egress FIFO. This allows the SPI-3 bus to still run and service the PHYs whose buffers are not full. Regardless of the Egress FIFO configuration for Store and Forward mode or Streaming mode, all complete packets received on the SPI-3 port for a full PHY will be discarded and PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 - Operation - VLAN Tag ...

  • Page 64

    ... Source Length/Type Address (2 bytes) (6 bytes) Destination Source Address Address (6 bytes) (6 bytes) Length/ Data Frame Type (46 to 1500 Check (2 bytes) bytes) Sequence (4 bytes) Data Frame Check (46 to 1500 bytes) Sequence (4 bytes) Length/Type Data (2 bytes) (46 to 1500 bytes) PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 ...

  • Page 65

    ... Egress FIFO and a count of the discarded frames are provided per channel. Note: The discard frame count is used to count frames discarded due to an Egress FIFO overflow condition and the SPI-3 Error pin assertion condition. PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 - Operation - Envoy-CE2 Device ...

  • Page 66

    ... Termination). The Egress FIFO indicates availability of a Frame to the Transmit MAC when a complete frame is stored in the Egress FIFO. The Transmit MAC reads the Egress FIFO and transmits the frame over the SMII/GMII transmit interface Operation - - PRELIMINARY TXC-06880-MB, Ed. 4 “Ethernet Full Duplex” on February 2005 ...

  • Page 67

    ... Transmit interface (Register 0x4084 Bit 28). These frames will be errored by forcing the MAC to append an incorrect CRC. 6.2.4.8 Preamble Length Option: The Preamble length of the transmitted Ethernet frame is programmable by the MAC. The default value is 7 bytes (Register 0x4004 Bits 12-15). PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 - Operation - Envoy-CE2 Device DATA SHEET ...

  • Page 68

    ... Six sets of counts for frame sizes that fall in a certain range. The ranges are 64 bytes 127 bytes, 128 to 255 bytes, 256 to 511 bytes, 512 to 1023 bytes, and 1024 to 1518 bytes. • Count of PAUSE frames originated via SPI-3 interface that are discarded (32 bit Operation - - PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 ...

  • Page 69

    ... Note: Carrier Sense and Collision detection status is indicated by the Ethernet PHY device to the Envoy-CE2 via the SMII and MII interface only. Please refer to the Serial Media Independent Interface (SMII) specification for further details. Following is an outline based on the Envoy-CE2 Configurable MAC. PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 - Operation - Per Ethernet ...

  • Page 70

    ... The number of retransmission attempts for excessive collisions is configurable. In the event a frame has been excessively deferred, the frame is discarded and will not be transmitted possible to configure the Envoy-CE2 not to discard an excessively deferred frame Operation - - th retransmission attempt is chosen as a uniformly where k = min(n,10). So, after the first PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 ...

  • Page 71

    ... PAUSE control frame. The pause_time parameter is used as the initial value of an internal count down timer. This timer is started as soon as the pause_time parameter is loaded into the count down timer. Envoy-CE2 will stay in this PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 - Operation - ...

  • Page 72

    ... Envoy-CE2, when the Ingress FIFOs reach the High Watermark and also generate a PAUSE control frame with a null value for pause_time, when the Ingress FIFO reaches the Low Watermark. This allows the Host to regulate the flow control mechanism Operation - - PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 ...

  • Page 73

    ... Configuration for Port 1 to Port 15 and for register addresses for Ethernet Statistics for Port 1 to Port 15. The SMIIREFCLK for each of the two CMACs must be active for these registers to operate correctly - even when the CMAC is configured in GMII mode. PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 - Memory Maps and Bit Descriptions - ...

  • Page 74

    ... Reserved Reserved CfgPins Reserved Reserved Reserved MII MGMT Configuration MII MGMT Command MII MGMT Address MII MGMT Control MII MGMT Status MII MGMT Indicators - 8 7 ResetControl ResetControl IrqMask IrqMask IrqStatus IrqStatus * Reserved GlobalCon trol StatIrqStatus StatIrqMask PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 0 ...

  • Page 75

    ... Memory Maps and Bit Descriptions - Description Reserved TXC Manufacturing ID: This field contains the manufacturer identification number for TranSwitch Corp., which is 0x06B. ENVOY ID: This field contains the Envoy-CE2 part number, TXC-06880. Device Version Level. This field is 1. Reserved processor. Reserved Reset Ethernet Port 0: Writing this bit will reset the Ethernet Port ...

  • Page 76

    ... Ethernet Port 1. Writing this bit will enable interrupts from Ethernet Port 1. Interrupt Mask for Ethernet Port 15: Writing this bit will mask the interrupt from Ethernet Port 15. Writing this bit will enable interrupts from Ethernet Port 15. Reserved - PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 ...

  • Page 77

    ... 31-16 PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 - Memory Maps and Bit Descriptions - Description Interrupt Mask for Ingress FIFO: Writing this bit will mask the interrupt from the Ingress FIFO. Writing this bit will enable interrupts from the Ingress FIFO. Interrupt Mask for SPI-3 Output Interface: Writing this bit will mask the interrupt from the SPI-3 output interface ...

  • Page 78

    ... CMAC B Pin Configuration: Reflection of the Configuration Pin for configuring MAC B (Pin - CFGCMACB[1:0 OFF GMII/MII Extended SMII SMII Reserved SPI-3 INPUT MODE Pin Configuration: Reflection of the Configuration Pin for configuring the SPI-3 Input Mode (CFGISPIMD SPI-3 in PHY (Slave) mode 1 - SPI-3 in Link (Master) mode - PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 ...

  • Page 79

    ... 31-5 0 PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 - Memory Maps and Bit Descriptions - Description SPI-3 OUTPUT MODE Pin Configuration: Reflection of the Configuration Pin for configuring the SPI-3 Output Mode (CFGOSPIMD SPI-3 in Slave mode 1 - SPI-3 in Master mode SPI-3 Bus Width Pin Configuration: Reflection of the Configuration Pin ...

  • Page 80

    ... Ethernet Port 0. Interrupt Status for Ethernet Ports Ethernet Statistics Reserved Interrupt Mask for Ethernet Port 0 Ethernet Statistics masks the interrupt from the Ethernet Statistics block for Ethernet Port 0. Interrupt Mask for Ethernet Ports Ethernet Statistics Reserved Reserved - PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 ...

  • Page 81

    ... RO 31-7 PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 - Memory Maps and Bit Descriptions - Description MII MGMT: CONFIGURATION REGISTER MGMT Clock Select: This field determines the clock frequency of the MGMT Clock (MDC). Consult Table below - MGMT Clock Select Encoding on how to program this field. MGMT Clock Select Encoding ...

  • Page 82

    ... Reserved MII MGMT: Data Write MII MGMT Write: When written, an MII MGMT write cycle is performed using the 16-bit data and the pre-configured PHY and Register addresses from the MII MGMT Address Register (0x0048). Reserved - PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 ...

  • Page 83

    ... 31-1 PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 - Memory Maps and Bit Descriptions - Description MII MGMT: Data Read MII MGMT Read Data: Following an MII MGMT Read Cycle, the 16-bit data can be read from this location. MII MGMT Read Register Address: Following an MII MGMT Read Cycle, the 5-bit register address of the register that was accessed can be read from this location ...

  • Page 84

    ... SPI-3 Input PTPA High Threshold SPI Input Error Status SPI-3 Input Interrupt Mask SPI-3 Output Config SPI-3 Output PHY Enable SPI-3 Output STPA Threshold SPI-3 Output Burst Size STPAEN PTPAEN Per Port Egress FIFO Full Status PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 0 ...

  • Page 85

    ... Reserved Reserved 27C0 27C4 Reserved PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 - Memory Maps and Bit Descriptions - 16 15 Per Port Egress FIFO Disabled Error Status Per Port Egress FIFO Start of Packet Error Status Reserved Per Port Egress FIFO Full Interrupt Mask ...

  • Page 86

    ... Egress FIFO reaches the STPA low threshold. This allows for a hysteresis in the STPA signal. For a bus width of 8 bits, the value is based on bytes. For a bus width of 16 bits, 2 bytes and a bus width of 32 bits, 4 bytes. Minimum value is 2. Reserved - PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 ...

  • Page 87

    ... RO 31-4 PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 - Memory Maps and Bit Descriptions - Description SPI-3 Input STPA High Threshold: Input SPI-3 near full high threshold for de-assertion of STPA. The high threshold is the fullness level and when reached by the Egress FIFO will de-assert STPA. The value is specified in terms of the SPI-3 bus width ...

  • Page 88

    ... SPI-3 Ingress Packet Errors indicated over the SPI-3 Error pin for Port 1. Clear on Read SPI-3 Input Packet Error Counter Port 15: Counter indicating the number of SPI-3 Ingress Packet Errors indicated over the SPI-3 Error pin for Port 15. Clear on Read. - PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 ...

  • Page 89

    ... RW 7-0 00000000 RO 31-8 PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 - Memory Maps and Bit Descriptions - Description SPI-3 Base Address: The 3 bit base address used to create the 8 bit SPI-3 port address for both SPI-3 Input and SPI-3 output. The base address bit programmable value and is assigned to the most significant 3 bits of the 8 bit SPI-3 address ...

  • Page 90

    ... Start of Packet and End of Packet in the same word (b) Assertion of the SPI-3 Error pin after a start of packet has been received. (c) An overflow occurred in the Egress FIFO. Packets are dropped in store and forward mode only (Egress FIFO Mode = 0). Clear on Read. - PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 ...

  • Page 91

    ... FFFF 2548 RW 15-0 FFFF RO 31-16 FFFF PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 - Memory Maps and Bit Descriptions - Description . . Egress FIFO Packet Drop Counter Port 15: The Egress FIFO Packet Drop Counter counts dropped packets for either of the following conditions: (a) Start of Packet and End of Packet in the same word (b) Assertion of the SPI-3 Error pin after a start of packet has been received ...

  • Page 92

    ... Reserved When the Port is in Streaming mode and the Egress FIFO reaches the programmed threshold, an indication is sent to the associated Configurable MAC block to transfer the Port’s Packet Data across the Ethernet interface. Reserved - PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 ...

  • Page 93

    ... RO 31-16 FFFF 2704 RC 15-0 0000 RO 31-16 FFFF PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 - Memory Maps and Bit Descriptions - Description . . Egress FIFO Streaming Threshold Port 15: Egress FIFO Streaming threshold in bytes for Port 15. The values are: 000 - 64 Bytes 001 - 128 Bytes 010 - 256 Bytes ...

  • Page 94

    ... Pause frames will halt or raise carrier will be de-asserted from that port. Note: Automatic pause frame generation needs to be enabled. Pause frame generation state is reached once the Pause high threshold is crossed. Reserved - PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 ...

  • Page 95

    ... RW 31-0 FFFFFFFF Ingress FIFO Full Interrupt Mask Per Port: FIFO full interrupt mask for PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 - Memory Maps and Bit Descriptions - Description Flow Control High Threshold CMAC B: This register sets the high threshold in multiples of 8 bytes, for Ports (serviced by Configurable MAC B), for generation of PAUSE frames or asserting raise carrier. In the event one of the Ethernet port’ ...

  • Page 96

    ... Ingress FIFO Near Full Status. If this bit interrupt will be generated. A Port will go into a near full condition when its Ingress FIFO level goes beyond the Pause Frame High Threshold value associated with the port. bits for the 16 Ingress FIFOs (one per port). - PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 ...

  • Page 97

    ... Source Address 5-6 .... 0x80 CFEP 0x84 LocCtrl1 0x88 Reserved 0x8C PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 - Memory Maps and Bit Descriptions - Port Ethernet Status and Configuration Register Map 16 15 MAC Configuration #1 MAC Configuration #2 IPG / IFG Half-Duplex Reserved Reserved Reserved ...

  • Page 98

    ... The port will “Loopback” all data received from the Egress FIFO controller to the Ingress FIFO controller, i.e. Data from the SPI-3 is looped back at the Ethernet interface Reserved Reset Tx Function The Transmit Function block is placed in reset. This block performs the frame transmission protocol. - “Envoy-CE2 PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 ...

  • Page 99

    ... PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 - Memory Maps and Bit Descriptions - Description Reset Rx Function The Receive Function block is placed in reset. This block performs the receive frame protocol. Reset Tx MAC Control The Transmit port MAC Control block is placed in reset. This block multiplexes data and Control frame transfers. It also responds to XOFF PAUSE Control frames ...

  • Page 100

    ... IPG between Back-to-Back Frames. This is the IPG parameter used exclusively in Full-Duplex and Half-Duplex modes when two transmit frames are sent back-to-back. Set this field to the number of bits of IPG desired. The default value is 0x60 (96d). Reserved - PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 ...

  • Page 101

    ... RW 30-24 0x40 RO 31 PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 - Memory Maps and Bit Descriptions - Description Minimum IFG Enforcement: This is a programmable field representing the minimum number of bits of IFG to enforce between frames. A frame whose IFG is less than that programmed is dropped or errored. The default value of 0x50 (80d) represents half of the nominal minimum IFG which is 160-bits ...

  • Page 102

    ... The Standard specifies that any collision after the tenth uses “210 - 1” as the maximum backoff time Alternate Binary Exponential Backoff Truncation: This field is used when Alternate Binary Exponential Backoff Enable is set. The value programmed is substituted for the Ethernet standard value of ten. Reserved - PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 ...

  • Page 103

    ... 30- PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 - Memory Maps and Bit Descriptions - Description MAXIMUM FRAME LENGTH REGISTER Maximum Frame Length: This field resets to 0x0600 (1536d), which represents the maximum frame size in both the transmit and receive directions. Reserved Reserved TEST REGISTER Shortcut Slot Time: This bit allows the slot time counter to expire regardless of the current count ...

  • Page 104

    ... SOURCE ADDRESS, 2nd Octet: This field holds the second octet of the source address. The second octet is stored in 23:16 and defaults to ‘0x00’. SOURCE ADDRESS, 1st Octet: This field holds the first octet of the source address. The first octet is stored in 31:24 and defaults to ‘0x00’. - PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 ...

  • Page 105

    ... RW 15-0 0 31-16 0 PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 - Memory Maps and Bit Descriptions - Description SOURCE ADDRESS REGISTER, PART 2 Reserved SOURCE ADDRESS, 6th octet: This field holds the sixth octet of the source address. The sixth octet is stored in 23:16 and defaults to ‘0x00’. ...

  • Page 106

    ... Disables internal statistics counters update 1 - Enables internal statistics counters to update Reserved Tx Source Address Substitute Enable: Transmitter Source Address Substitution Enable Substitute the outgoing source address field in the Ethernet header with the programmed source address in the MAC (Addresses 0x4040 and 0x4044). - PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 ...

  • Page 107

    ... PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 - Memory Maps and Bit Descriptions - Description Rx CRC Remove: Configures the removal of the CRC (FCS) bytes from the Ethernet frame received at the Rx interface destined for the SPI-3 output interface Remove CRC GTx Clock Select: The Rx clock is used when connecting the Envoy-CE2 to another MAC in a MAC-to-MAC configuration ...

  • Page 108

    ... Flow Control Mode: Configures the flow control mode Raise Carrier Mode 1 - Pause Frames Half-Duplex Flow Control Duration: Configures the Half Duplex flow control duration Raise Carrier stopped after 128K byte times 1 - Continuous Raise Carrier flow control till congestion is relieved - PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 ...

  • Page 109

    ... Depends on CMAC Configurati on pins 31-2 0 PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 - Memory Maps and Bit Descriptions - Description Reserved PAUSE Frame Received: Status indication that an error free, unicast, or multicast PAUSE frame has been received. Rx Frame Discarded: Status indication of a frame discard due to lack of FIFO memory resource (overflow) ...

  • Page 110

    ... FCS octets). Rx 512 to 1023 Octet Packets: The total number of packets (including bad packets) received that were between 512 and 1023 octets in length inclusive (excluding framing bits but including FCS octets). - PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 ...

  • Page 111

    ... RC 31-0 0 PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 - Memory Maps and Bit Descriptions - Description Rx 1024 to 1518 Octet Packets: The total number of packets (includ- ing bad packets) received that were between 1024 and 1518 octets (1522 for VLAN tagged packets) in length inclusive (excluding framing bits but including FCS octets) ...

  • Page 112

    ... Note: Packets less than 64 octets but with a bad FCS are counted in the Tx Fragment Packets counter Octet Packets: The total number of packets (including bad pack- ets) transmitted successfully that were 64 octets in length (excluding framing bits but including FCS octets). - PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 ...

  • Page 113

    ... RC 31-0 0 6088 RC 31-0 0 PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 Description 127 Octet Packets: The total number of packets (including bad packets) transmitted successfully that were between 65 and 127 octets in length inclusive (excluding framing bits but including FCS octets). Tx 128 to 255 Octet Packets: The total number of packets (including ...

  • Page 114

    ... FCS octets), and had a bad Frame Check Sequence (FCS). This count will include packets truncated by the MAC because they were longer than MAX octets. MAX octets value is the “Maximum Frame Length” value programmed in the MAC. PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 ...

  • Page 115

    ... RC 7 31-8 0 PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 Description Tx Drop Frame: The total number of transmitted packets which were aborted due to an under-run of the Egress FIFO, i.e., lack of system resources. When this is detected, the MAC transmitter will jam the packet and insert an incorrect FCS. ...

  • Page 116

    ... Values shown are for reference only. 2. Identification of the solder ball A1 corner is contained within this shaded zone. This package corner may be a 90° angle, or chamfered for A1 identification. 3. Size of array 26, JEDEC code MO-151 ACKAGE E 0. Places E2 TRANSWITCH TXC-06880BIOG TXC-06880BROG -D1- Note 2 D1 Dimension (Note 1) A (Nom (Nom) b (Ref.) D1 (Nom) D2 ...

  • Page 117

    ... Part Number: TXC-06880BIOG 580-lead plastic ball grid array (PBGA) package, TXC-06880BROG 580-lead plastic ball grid array (PBGA) package, ® PHAST -12P Device (STM-4/OC-12 SDH/SONET Overhead Terminator with CDB/PPP UTOPIA/POS-PHY Interface). The PHAST-12P is a highly integrated SDH/SONET overhead terminator device designed for ATM cell and PPP packet payload mappings. A single PHAST-12P can terminate four individual STM-1/OC-3 lines or a single STM-4/OC-12 line ...

  • Page 118

    ... Fax: 20 7417 7500 Tel: Fax: 3 3438 3698 Tel: Tel: Fax: (303) 397-2740 Web: Tel: Fax Web: S OURCES (212) 642-4900 www.ansi.org (415) 561-6275 www.atmforum.com 20 7837 7882 3 3438 3694 (800) 854-7179 (within U.S.A.) (303) 397-7956 (outside U.S.A.) www.global.ihs.com www.etsi.org PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 ...

  • Page 119

    ... Corporate Place Rm 3A184 Piscataway, NJ 08854-4157 TTC (Japan): TTC Standard Publishing Group of the Telecommunication Technology Committee Hamamatsu-cho Suzuki Building 1-2-11, Hamamatsu-cho, Minato-ku Tokyo 105-0013, Japan PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 Envoy-CE2 Device DATA SHEET TXC-06880 Tel: (800) 669-6857 (within U.S.A.) Tel: (903) 769-3717 (outside U.S.A.) ...

  • Page 120

    ... Envoy-CE2 Device DATA SHEET TXC-06880 Memory Maps and Bit Descriptions - - NOTES - - PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 ...

  • Page 121

    ... PRELIMINARY TXC-06880-MB, Ed. 4 February 2005 - Memory Maps and Bit Descriptions - - NOTES - TranSwitch reserves the right to make changes to the product(s) or circuit(s) described herein without notice. No liability is assumed as a result of their use or application. TranSwitch assumes no liability for TranSwitch applications assistance, customer product design, soft- ware performance, or infringement of patents or services described herein ...

  • Page 122

    ... VLSI semiconductor solutions to communications network equipment manufacturers. Serving three fast-growing end-markets; Public Network Infrastructure, Internet Specializing in the design, development, marketing and support of these networking semiconductor solutions, which we call TranSwitch Corporation • 3 Enterprise Drive Tel: 203-929-8810 • Infrastructure and Wide Area Networks (WANs). ...