TXC-06880BIOG Transwitch Corporation, TXC-06880BIOG Datasheet - Page 86

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TXC-06880BIOG

Manufacturer Part Number
TXC-06880BIOG
Description
Manufacturer
Transwitch Corporation
Datasheet

Specifications of TXC-06880BIOG

Operating Supply Voltage (typ)
1.8/3.3V
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TXC-06880BIOG
Manufacturer:
SAMWHA
Quantity:
34 000
Envoy-CE2 Device
DATA SHEET
TXC-06880
2000
2004
2008
8 6 o f 12 2
(hex)
Addr
RO
RW
RO
RW
RO
RW
RO
Mode
15-0
16
17
19-18
20
21
31-22
15-0
31-16
7-0
31-8
range
Egress/Ingress FIFO and SPI-3 Input/Output, Status, and Control Register Map
Bit
0
0
00
1
1
00000000
0000
00000000
value after
Default
reset
-
Memory Maps and Bit Descriptions
SPI-3 Input Configuration
Reserved
SPI-3 Input Single-PHY Enable: The SPI-3 Single-PHY mode enable
bit.
0 - Multi-PHY
1 - Single-PHY
SPI-3 Input Aggregation Mode Enable: The Aggregation Mode Enable
bit for SPI-3 Input.
0 - Normal mode
1 - Aggregate mode
Aggregate Mode TAG Position: The Ethernet Aggregate Mode Tag
Position. This indicates the byte position in the Aggregate Tag word (4
bytes long), which indicates the PHY number of the packet.
SPI-3 Input Parity Mode: SPI-3 Input interface parity mode.
0 - Even parity
1 - Odd parity
SPI-3 Input Parity Enable: SPI-3 Input interface parity checking enable
bit.
0 - Parity checking not enabled
1 - Parity checking enabled
Reserved
SPI-3 Input PHY/Port Enable Per Port: SPI-3 Input PHY/Port Enable
bits for the 16 SPI-3 Input ports (one per port). Bit 0 = Port 0, Bit 1 = Port
1..... Bit 15 = Port 15.
Reserved
SPI-3 Input STPA Low Threshold: Input SPI-3 near full low threshold
for assertion of STPA. Once STPA is de-asserted because the Egress
FIFO reached the SPI-3 high threshold (SISHT), STPA will be asserted
when the Egress FIFO reaches the STPA low threshold. This allows for
a hysteresis in the STPA signal. For a bus width of 8 bits, the value is
based on bytes. For a bus width of 16 bits, 2 bytes and a bus width of 32
bits, 4 bytes. Minimum value is 2.
Reserved
Description
-
PRELIMINARY TXC-06880-MB, Ed. 4
February 2005

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