LU82551QM Intel, LU82551QM Datasheet
LU82551QM
Specifications of LU82551QM
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LU82551QM Summary of contents
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... Hazardous Substances (RoHS)-banned materials, is available at: ftp://download.intel.com/design/packtech/ material_content_IC_Package.pdf#pagemode=bookmarks In addition, this device has been tested and conforms to the same parametric specifications as previous versions of the device. For more information regarding lead-free products from Intel Corporation, contact your Intel Field Sales Rerepresentative. Datasheet — ...
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... Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right ...
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Contents 1.0 Introduction......................................................................................................................... 1 1.1 Overview ............................................................................................................... 1 1.2 Byte Ordering ........................................................................................................ 1 1.3 References ............................................................................................................ 1 1.4 Product Ordering Codes........................................................................................ 2 2.0 Architectural Overview ....................................................................................................... 3 2.1 Parallel Subsystem Overview................................................................................ 3 2.2 FIFO Subsystem Overview ................................................................................... 4 2.3 Manageability ...
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Networking Silicon 5.8.1 Full Duplex ............................................................................................. 35 5.8.2 Flow Control ........................................................................................... 36 5.8.3 Address Filtering Modifications .............................................................. 36 5.8.4 VLAN Support ........................................................................................ 36 5.9 Media Independent Interface (MII) Management Interface ................................. 36 6.0 Physical Layer Functional Description ............................................................................. ...
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CardBus Card Information Structure (CIS) Pointer ................................ 56 9.1.12 PCI Subsystem Vendor ID and Subsystem ID Registers.......................56 9.1.13 Capability Pointer ................................................................................... 57 9.1.14 Interrupt Line Register............................................................................ 57 9.1.15 Interrupt Pin Register ............................................................................. 57 9.1.16 Minimum Grant Register ........................................................................ 58 ...
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Networking Silicon 11.0 PHY Unit Registers .......................................................................................................... 79 11.1 MDI Registers ............................................................................................. 79 11.1.1 Register 0: Control Register .................................................................. 79 11.1.2 Register 1: Status Register ................................................................... 80 11.1.3 Register 2: PHY Identifier Register ....................................................... 81 ...
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... Controller, a member of the 8255x Fast Ethernet Controller family. 1.1 Overview The 82551QM is an evolutionary addition to Intel’s family of 8255x controllers. It provides excellent performance by offloading TCP, UDP and IP checksums and supports TCP segmentation off-load for operations such as Large Send. Its optimized 32-bit interface and efficient scatter-gather bus mastering capabilities enable the 82551QM to perform high speed data transfers over the PCI bus or CardBus ...
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... Combined Footprint LOM Design Guide. Intel Corporation 1.4 Product Ordering Codes The product ordering code for the 82551QM is: • GD82551QM (Leaded) • LU82551QM (Lead Free) Device Stepping LU82551QM LU82551QM GD82551QM GD82551QM Figure 1. 82551QM Component Markings Legend: ...
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... Architectural Overview ® The Intel 82551QM is divided into five main subsystems: a parallel subsystem, a FIFO subsystem, the manageability subsystem, a 10/100 Mbps Carrier Sense Multiple Access with Collision Detect (CSMA/CD) unit, and a 10/100 Mbps physical layer (PHY) unit. 2.1 Parallel Subsystem Overview ...
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... Manageability Subsystem Overview The 82551QM’s Manageability subsystem supports bi-directional ASF, version 1.0. In addition, it provides a Total Cost of Ownership (TCO) interface that enables connection with alerting and management controllers such as the Intelligent Platform Management Interface (IPMI) solutions and Baseboard Management Controllers (BMCs). 2.4 10/100 Mbps Serial CSMA/CD Unit Overview The 82551QM’ ...
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... Performance Enhancements All of Intel’s Fast Ethernet controllers have the ability to support full wire speeds. The 82551QM has been designed to provide improved networking throughput. Performance is limited to the system’s ability to feed data to the network controller. As networks grow, the task of servicing the network becomes a large burden on the platform. ...
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Networking Silicon 3.3 Hardware Integrity Support Cabling problems are a common cause for network downtime situations. Hardware Integrity (HWI) can help reduce this by locating cabling problems, which reduces Total Cost of Ownership (TCO). It uses transmission line ...
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Signal Descriptions 4.1 Signal Type Definitions Table 2. Signal Type Descriptions Type Name IN Input OUT Output TS Tri-State STS Sustained Tri-State OD Open Drain AI Analog Input AO Analog Output B Bias Digital Power DPS Supply Analog Power ...
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Networking Silicon 4.2 PCI Bus and CardBus Interface Signals 4.2.1 Address and Data Signals Table 3. Address and Data Signals Symbol Type AD[31:0] TS C/BE#[3:0] TS PAR TS 4.2.2 Interface Control Signals Table 4. Interface Control Signals Symbol ...
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Table 4. Interface Control Signals Symbol Type IDSEL IN DEVSEL# STS REQ# TS GNT# IN INTA# OD SERR# OD PERR# STS 4.2.3 System and Power Management Signals Table 5. System and Power Management Signals Symbol Type CLK IN IN/OUT CLK_RUN# ...
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Networking Silicon Table 5. System and Power Management Signals Symbol Type CSTSCHG/ OUT WOL ISOLATE# IN ALTRST VIO IN 4.3 Local Memory Interface Signals Note: All unused Flash Address and Data pins MUST be left floating. ...
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Table 6. Local Memory Interface Signals Symbol Type FLA12/ IN/OUT MCNTSM# FLA11/MINT IN/OUT FLA10/ IN/OUT MRING# FLA9/MRST IN/OUT FLA8/ IN/OUT IOCHRDY FLA7/ IN/OUT CLKEN FLA6:2 OUT FLA1/ TS AUXPWR FLA0/ TS PCIMODE# EECS OUT Datasheet Name and Function Flash Address ...
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Networking Silicon Table 6. Local Memory Interface Signals Symbol Type FLCS# OUT FLOE# OUT FLWE# OUT MDMCS# OUT 4.4 System Management Bus (SMB) Interface Signals Table 7. System Management Bus (SMB) Interface Signals Symbol SMBDATA SMBCLK SMB_ALERT#/ LAN_PWR_GOOD ...
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Test Port Signals Table 8. Test Port Signals Symbol Type TEST IN TCK TEXEC IN TO OUT Note: These test port signals are not JTAG compatible result, a BSDL file is not required. 4.6 ...
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Networking Silicon Table 9. PHY Signals Symbol Type RBIAS100 B RBIAS10 B VREF B a. Based on some board designs, RBIAS100 and RBIAS10 values may need to be increased/decreased to com- pensate for high/low MDI transmit amplitude. See ...
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Media Access Control Functional Description 5.1 Device Initialization The 82551QM has six sources for initialization. They are listed according to their precedence: 1. Internal Power-on Reset (POR) 2. ALTRST# pin 3. RST# pin 4. ISOLATE# pin 5. Software Reset ...
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Networking Silicon Table 11. Initialization Effects Internal POR Power management event reset Statistic counters reset Sampling of configuration input pins 5.1.2 Initialization Effects on TCO Functionality The 82551QM has the ability to be controlled by two masters, the ...
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To perform these actions, the 82551QM is controlled and examined by the CPU through its control and status structures and registers. Some of these structures reside in the 82551QM and some reside in system memory. For access to the 82551QM’s ...
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Networking Silicon Figure 2. CSR I/O Read Cycle CLK FRAME# AD C/BE# IRDY# TRDY# DEVSEL# STOP# Read Accesses: The CPU, as the initiator, drives address lines AD[31:0], the command and byte enable lines C/BE#[3:0] and the control lines ...
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Write Accesses: The CPU, as the initiator, drives the address lines AD[31:0], the command and byte enable lines C/BE#[3:0] and the control lines IRDY# and FRAME#. It also provides the 82551QM with valid data on each data access immediately after ...
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Networking Silicon Figure 5. Flash Buffer Write Cycle CLK FRAME# AD C/BE# IRDY# TRDY# DEVSEL# STOP# Write Accesses: The CPU, as the initiator, drives the address lines byte enable lines C/BE#[3:0] and 82551QM with valid data immediately after ...
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Retry Premature Accesses The 82551QM responds with a Retry to any configuration cycle accessing the 82551QM before the completion of the automatic read of the EEPROM. The 82551QM may continue to Retry any configuration accesses until the EEPROM read ...
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Networking Silicon System Error: The 82551QM reports parity error during the address phase using the SERR# pin. If the SERR# Enable bit in the PCI Configuration Command register or the Parity Error Response bit is not set, the ...
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Figure 8. Memory Write Burst Cycle CLK FRAME# AD C/BE# IRDY# TRDY# DEVSEL# The CPU provides the 82551QM with action commands and pointers to the data buffers that reside in host main memory. The 82551QM independently manages these structures and ...
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Networking Silicon 5.2.1.2.1 Memory Write and Invalidate The 82551QM has four Direct Memory Access (DMA) channels. Of these four channels, the Receive DMA is used to deposit the large number of data bytes received from the link into ...
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When the arbitration counter’s feature is enabled (in other words, the Transmit DMA Maximum Byte Count value is set in the Configure command), the 82551QM switches to other pending DMAs on cache line boundary only. This feature is not ...
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Networking Silicon 5.3 PCI Power Management The 82551QM supports a larger set of wake-up packets and the capability to wake the system on a link status change from a low power state. These added power management enhancements enable ...
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D1 Power State For a device to meet the D1 power state requirements, as specified in the Advanced Configuration and Power Interface (ACPI) Specification, Revision 1.0, it must not allow bus transmission or interrupts; however, bus reception is allowed. ...
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Networking Silicon 5.3.1.4.1 Auxiliary Power Signal The 82551QM senses whether it is connected to the PCI power supply auxiliary power supply (V ) through the FLA1/AUXPWR pin. The auxiliary power detection pin (multiplexed AUX with ...
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If PME is enabled (in the PCI power management registers), the RST# signal does not affect any PME related circuits (in other words, the CSTSCHG registers (CardBus only), PCI power management registers, and the wake-up packet would not be affected). ...
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Networking Silicon The following tables list the functionality at the different power states for the 82551QM. Table 13. Functionality at the Different Power States Power State D0u D0a (with power) Dx (x>0 without PME#) 5.3.2 ...
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This allows the 82551QM to handle various packet types. In general, the 82551QM supports programmable filtering of any packet in the first 128 bytes. When the 82551QM is in one of the low power states, it searches for a predefined ...
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Networking Silicon • An ALTRST# is completed. • The 82551QM reads the EEPROM and the WOL bit is set. When the 82551QM is in WOL mode: • The 82551QM scans incoming packets for a Magic Packet. When it ...
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Note: Flash accesses must always be assembled or disassembled by the 82551QM whenever the access is greater than a byte-wide access. Due to slow access times to a typical Flash and to avoid violating PCI bus holding specifications (no more ...
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... Alerting Poll 4 Event Code Alerting Reset/Power Descriptor Address Alerting Reset Descriptors ARP Enable Reserved Device ID (high byte) Reserved Intel Boot Agent Configuration Low Byte (Bits 7 – 0) Ethernet Individual Address Byte 1 Ethernet Individual Address Byte 3 Ethernet Individual Address Byte 5 Compatibility Byte 0 Connectors ...
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Table 14. EEPROM Address Map (Continued) Word 32h – 3Eh 3Fh 64-word EEPROM Checksum (high byte) 40h:F7h F8h:FEh FFh 256-word EEPROM Checksum, high byte Note: Refer to the 82551QM/ER/IT EEPROM Map and Programming Information for more details. 5.8 10/100 Mbps ...
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Networking Silicon 5.8.2 Flow Control The 82551QM supports IEEE 802.3x frame-based flow control frames in both full duplex and half duplex switched environments. The 82551QM flow control feature is not intended to be used in shared media environments. ...
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Physical Layer Functional Description 6.1 100BASE-TX PHY Unit 6.1.1 100BASE-TX Transmit Clock Generation A 25 MHz crystal MHz oscillator is used to drive the PHY unit’s X1 and X2 pins. The PHY unit derives its internal ...
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Networking Silicon 6.1.4 100BASE-TX Link Integrity Auto-Negotiation The 82551QM Auto-Negotiation function automatically configures the device to the technology, media, and speed to operate with its link partner. Auto-Negotiation is described in IEEE specification 802.3u, clause 28. The PHY ...
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Link Integrity and Full Duplex The link integrity in 10 Mbps works with link pulses. The PHY unit senses and differentiates those link pulses from fast link pulses and from 100BASE-TX idles. The link beat pulse is also ...
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Networking Silicon Figure 11. Auto-Negotiation and Parallel Detect Auto-Negotiation capable = 0 6.4 LED Description The PHY unit supports three LED pins to indicate link status, network activity and network speed. Each pin can source 10 mA. • ...
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Figure 12. Two and Three LED Schematic Diagram Datasheet Networking Silicon — 82551QM LILED# R ACTLED# SPDLED# 82551QM LILED ACTLED# SPDLED# vcc ...
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Networking Silicon Note: This page intentionally left blank. 42 Datasheet ...
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Modem Functionality The local port mimics the standard 8-bit interface of a modem to the host system and emulates a 16550 Universal Asynchronous Receiver/Transceiver (UART) modem interface. The modem interface includes the following: • 8-bit data bus: FLD7:0 • ...
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Networking Silicon 7.3.1 Programming Details For designs that use both Flash and modem devices, the 82551QM supports the coexistence of BootROM accesses (for Preboot eXtension Environment [PXE] code) and modem: 1. Set the EEPROM’s MDM bit. 2. Clear ...
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... The 82551QM supports the Alert Standard Format (ASF) Specification, version 1.0 to monitor the health of systems connected to the network, including desktop, workstation and server systems. Intel’s ASF hardware and software enables all systems on the network to report advanced warning and system failure messages to a network management console, in the powered-up, powered-down, and pre-boot state ...
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... Some common SMB, version 1.0 sensors available on the market: • Voltage • Temperature • Fan Tach In addition, Intel’s 82551QM includes support for the following remote control operations: • Presence ping/pong • System capability request/response • System state request/response • ...
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Watchdog A watchdog packet is sent when the watchdog timer expires. Software can use these registers to indicate the state of the system. For example, the watchdog timer can be set and enabled upon initial power up. If the ...
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Networking Silicon Note: This page intentionally left blank. 48 Datasheet ...
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Configuration Registers The 82551QM acts as both a master and a slave on the PCI bus master, the 82551QM interacts with the system main memory to access data for transmission or deposit received data slave, ...
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Networking Silicon 9.1.2 PCI Command Register The 82551QM Command register at word address 04h in the PCI configuration space provides control over the 82551QM’s ability to generate and respond to PCI cycles register, the 82551QM is logically disconnected ...
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Table 15. PCI Command Register Bits Bits Name 2 Bus Master 1 Memory Space 0 I/O Space 9.1.3 PCI Status Register The 82551QM Status register is used to record status information for PCI bus related events. The format of this ...
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Networking Silicon Table 16. PCI Status Register Bits Bits Name 28 Received Target Abort 27 Signaled Target Abort 26:25 DEVSEL# Timing 24 Parity Error Detected 23 Fast Back-to-Back 20 Capabilities List 19:16 Reserved 9.1.4 PCI Revision ID Register ...
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PCI Cache Line Size Register In order for the 82551QM to support the Memory Write and Invalidate (MWI) command, the 82551QM must also support the Cache Line Size (CLS) register in PCI Configuration space. The register supports only cache ...
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Networking Silicon in a device independent manner, the base registers for this mapping are placed in the predefined header portion of configuration space. Device drivers can then access this configuration space to determine the mapping of a particular ...
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CSR I/O Mapped Base Address Register The 82551QM requires one BAR for I/O mapping. Software determines which BAR, I/O or memory, is used to access the 82551QM CSR registers. The I/O space for the 82551QM CSR I/O BAR is ...
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Networking Silicon 9.1.9.4 Expansion ROM Base Address Register The Expansion ROM has a memory space and its BAR is a Dword register that supports a 128 KB memory via the 82551QM local bus. The Expansion ...
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The 82551QM provides support for configurable Subsystem Vendor ID and Subsystem ID fields. After hardware reset is de-asserted, the 82551QM automatically reads addresses Ah through Ch of the EEPROM. The first of these 16-bit values is used for controlling various ...
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Networking Silicon 9.1.16 Minimum Grant Register The Minimum Grant (Min_Gnt) register is an optional read only register for bus masters and is not applicable to non-master devices. It defines the amount of time the bus master wants to ...
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Table 20. Power Management Capability Register Bits Default 0b (PCI (CardBus 18:16 010b 9.1.21 Power Management Control/Status Register (PMCSR) The Power Management Control/Status is a word register used to determine and change the current ...
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Networking Silicon 9.1.22 Data Register The data register is an 8-bit read only register that provides a mechanism for the 82551QM to report state dependent maximum power consumption and heat dissipation. The value reported in this register depends ...
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Figure 21. Modem PCI Configuration Registers Max_Lat Modem Power Management Capabilities Reserved The modem configuration registers define the resources required by the modem function meaningful in a multifunction card design only. Some of the modem configuration registers are ...
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Networking Silicon 9.2.3 Modem Status Register The Modem Status field is a 16-bit word register. It provides basic track of CardBus related events. All bits are cleared by RST#. Table 24. Modem Status Register Bits Default 15 0 ...
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Modem Memory Base Address Register The Modem Memory BAR is a Dword register that specifies the memory base address for accessing the 82551QM’s modem port. The required memory space is 4 KB. The memory space is used for both ...
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Networking Silicon 9.2.14 Modem Power Management Control/Status Register The Modem Power Management Control/Status Register is a word register used to manage the modem’s power management state. It also enables and monitors power management events. The Modem ...
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Control/Status Registers 10.1 LAN (Ethernet) Control/Status Registers The 82551QM’s Control/Status Register (CSR) is illustrated in the Figure 22. Control/Status Register D31 Upper Word SCB Command Word EEPROM Control Register PMDR Reserved NOTE: In Figure 22 above, SCB is defined ...
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Networking Silicon MDI Control Register: The MDI Control register allows the CPU to read and write information from the PHY unit (or an external PHY component) through the Management Data Interface. Receive DMA Byte Count: The Receive DMA ...
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Table 27. System Control Block Status Word Bits Name 8 FCP 7:6 CUS 5:2 RUS 1:0 Reserved 10.1.2 System Control Block Command Word Commands for the 82551QM’s Command and Receive units are placed in this register by the CPU. Table ...
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Networking Silicon 10.1.6 EEPROM Control Register The EEPROM Control Register is a 32-bit field that enables a read from and a write to the external EEPROM. 10.1.7 Management Data Interface Control Register The Management Data Interface (MDI) Control ...
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Power Management Driver Register The 82551QM provides an indication in memory and I/O space that a wake-up event has occurred located in the Power Management Driver (PMDR). The PMDR is used for CardBus mode only. Table 30. ...
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Networking Silicon Note: The PMDR is initialized at ALTRST# reset only. 10.1.11 General Control Register The General Control register is a byte register and is described below. The General Control register is used in CardBus mode only. Table ...
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These CardBus registers are used by software to determine which event has occurred, to manage the event, and to control the CSTSCHG signal. The 82551QM supports only the interrupt and general wake-up event bits in the card status change 1 ...
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Networking Silicon 10.1.13.2 LAN Function Event Mask Register The Function Event Mask register masks CSTSCHG and INTA# assertion. Table 34. LAN Function Event Mask Register Bits Function 31:16 Reserved 15 INTR 14 WKUP 13:7 Reserved PWM 6:5 BAM ...
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Table 35. LAN Function Present State Register Bits Function 3 Reserved 2 Reserved 1 Reserved 0 Reserved 10.1.13.4 LAN Force Event Register The Force Event register simulates status change events for troubleshooting purposes. This register provides the ability to simulate ...
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Networking Silicon Table 37. Statistical Counters ID Counter 12 Transmit Underrun Errors 16 Transmit Lost Carrier Sense (CRS) 20 Transmit Deferred 24 Transmit Single Collisions 28 Transmit Multiple Collisions 32 Transmit Total Collisions 36 Receive Good Frames 40 ...
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Table 37. Statistical Counters ID Counter 64 Flow Control Transmit Pause 68 Flow Control Receive Pause 72 Flow Control Receive Unsupported 76 Receive TCO Frames 78 Transmit TCO Frames The Statistical Counters are initially set to zero by the 82551QM ...
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Networking Silicon 10.3.1 Modem Base Memory Addressing The modem base memory addressing is an 8-byte address space. There are three types of address spaces: 1. Modem chipset address space Modem function address space: 80h ...
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Modem Function Event Mask Register The Modem Function Event Mask register masks CSTSCHG and INTA# assertion as listed in Table 40. Table 40. Modem Function Event Mask Register Bits Function 31:16 Reserved 15 INTR 14 WKUP 13:7 Reserved PWM ...
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Networking Silicon Table 41. Modem Function Present State Register Bits Function 2 Reserved 1 Reserved 0 Reserved 10.3.3.4 Modem Force Event Register The Modem Force Event register simulates status change events for troubleshooting purposes identical to ...
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PHY Unit Registers The 82551QM provides status and accepts management information via the Management Data Interface (MDI) within the CSR space. Acronyms mentioned in the registers are defined as follows self cleared RO - read only E ...
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Networking Silicon Table 42. Register 0: Control Bit(s) Name 11 Power-Down 10 Reserved 9 Restart Auto- Negotiation 8 Duplex Mode 7 Collision Test 6:0 Reserved 11.1.2 Register 1: Status Register Table 43. Register 1: Status Bit(s) Name 15 ...
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Table 43. Register 1: Status Bit(s) Name 3 Auto-Negotiation Ability 2 Link Status 1 Jabber Detect 0 Extended Capability 11.1.3 Register 2: PHY Identifier Register Table 44. Register 2: PHY Identifier Bit(s) Name 15:0 PHY ID (high byte) 11.1.4 Register ...
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Networking Silicon 11.1.6 Register 5: Auto-Negotiation Link Partner Ability Register Table 47. Auto-Negotiation Link Partner Ability Bit(s) Name 15 Next Page 14 Acknowledge 13 Remote Fault 12:5 Technology Ability Field 4:0 Selector Field 11.1.7 Register 6: Auto-Negotiation Expansion ...
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MDI Register 11.3.1 Register 16: PHY Unit Status and Control Register Table 49. PHY Unit Status and Control Bit(s) Name 15:14 Reserved 13 Carrier Sense Disconnect Control 12 Transmit Flow Control Disable 11 Receive De- Serializer ...
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Networking Silicon Table 50. Register 17: PHY Unit Special Control Bit(s) Name 12 Force 34 Transmit Pattern 11 Good Link 10 Reserved 9 Transmit Carrier Sense Disable 8 Disable Dynamic Power-Down 7 Auto-Negotiation Loopback 6 MDI Tri-State 5 ...
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Register 20: 100BASE-TX Receive Disconnect Counter Table 53. Register 20: 100BASE-TX Receive Disconnect Counter Bit(s) Name 15:0 Disconnect Event 11.3.6 Register 21: 100BASE-TX Receive Error Frame Counter Table 54. Register 21: 100BASE-TX Receive Error Frame Counter Bit(s) Name 15:0 ...
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Networking Silicon 11.3.10 Register 25: 10BASE-T Transmit Jabber Detect Counter Table 58. Register 25: 10BASE-T Transmit Jabber Detect Counter Bit(s) Name 15:0 Jabber Detect Counter 11.3.11 Register 26: Equalizer Control and Status Register Table 59. Register 26: Equalizer ...
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Register 28: MDI/MDI-X Control Register Table 61. Register 28: MDI/MDI-X Control Bit(s) Name 15:8 Reserved Auto Switch 7 Enable 6 Switch 5 Status Auto Switch 4 Complete 3:0 Resolution Timer 11.3.14 Register 29: Hardware Integrity Control Register Table 62. ...
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Networking Silicon Table 62. Register 29: Hardware Integrity Control Bit(s) Name 12:11 Reserved 10:9 LowZ/HighZ 8:0 Distance 88 Description These bits are reserved and should be set to 0b. This field of bits indicates either a short (Low ...
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Electrical and Timing Specifications Note: This section contains information on products in sampling and early production phase of development. Do not finalize a design with this information. Revised information will be published when the product becomes available. 12.1 Absolute ...
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Networking Silicon 12.2 DC Specifications Table 63. General DC Specifications Symbol Parameter V Supply Voltage CC Periphery Clamp V IO Voltage Power Supply (10BASE- Power Supply (100BASE-TX) NOTES: 1. Preferably, VIO should ± ...
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Table 64. PCI/CardBus Interface DC Specifications CLK Pin Capacitance C CLKP C IDSEL Pin Capacitance IDSEL L Pin Inductance PINP PME# Input Leakage I OFFPME Current NOTES: 1. These values are only applicable in 3.3 V signaling environments. Outside of ...
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Networking Silicon Table 67. LED Voltage/Current Characteristics Symbol Parameter V Output High Voltage OHLED V Output Low Voltage OLLED Table 68. 100BASE-TX Voltage/Current Characteristics Symbol Parameter Input Differential R ID100 Impedance Input Differential V IDA100 Accept Peak Voltage ...
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Table 70. Digital I/O Characteristics Symbol Table 71. Crystal Input One (X1) Characteristics Symbol 12.3 AC Specifications Table 72. AC Specifications for PCI Signaling Symbol Parameter Switching Current High I OH(AC) (Test ...
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Networking Silicon Table 73. AC Specifications for CardBus Signaling Symbol Parameter CardBus Output t RCB Rise Time CardBus Output t FCB Fall Time 12.4 Timing Specifications 12.4.1 Clocks Specifications 12.4.1.1 PCI/CardBus Clock Specifications The 82551QM uses the PCI ...
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X1 Specifications X1 serves as a signal input from an external crystal or oscillator. requirements from this signal. Table 75. X1 Clock Specifications Symbol T8 Tx1_dc T9 Tx1_pr 12.4.2 Timing Parameters 12.4.2.1 Measurement and Test Conditions Figure 24, Figure ...
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Networking Silicon Figure 25. Input Timing Measurement Conditions CLK INPUT Table 76. Measure and Test Condition Parameters V step V step Input Signal Edge NOTE: Input test is done with 0.1V for testing input timing. 96 V_test T_su ...
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PCI/CardBus Timings Table 77. PCI/CardBus Timing Parameters Symbol PCI CLK to Signal Valid Delay T14 t val CardBus CLK to Signal Valid Delay PCI CLK to Signal Valid Delay (point- T15 t val(ptp) to-point) T16 t Float to Active ...
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Networking Silicon • FLA8 acts as IOCHRDY asynchronous input in modem mode. Table 78. Flash Timing Parameters Symbol T35 t Flash Read/Write Cycle Time flrwc T36 t FLA to Read FLD Setup Time flacc T37 t FLCS# to ...
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Figure 26. Flash/Modem Timings for a Read Cycle FLADDR FLCS# FLOE# FLDATA-R IOCHRDY Figure 27. Flash/Modem Timings for a Write Cycle FLADDR FLCS# FLWE# FLDATA-W IOCHRDY Datasheet Networking Silicon — 82551QM Address Stable T35 T37 T38 T36 Data In T49 ...
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Networking Silicon 12.4.2.4 EEPROM Interface Timings The 82551QM is designed to support a standard 64x16 or 256x16 serial EEPROM. provides the timing parameters for the EEPROM interface signals. The timing parameters are illustrated in Figure 28. Table 79. ...
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PHY Timings Table 80. 10BASE-T Normal Link Pulse (NLP) Timing Parameters Symbol T56 T NLP Width nlp_wid T57 T NLP Period nlp_per Figure 29. 10BASE-T Normal Link Pulse (NLP) Timings Normal Link Pulse Table 81. Auto-Negotiation Fast Link Pulse ...
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Networking Silicon Table 82. 100Base-TX Transmitter AC Specification Symbol TDP/TDN Differential T64 T jit Output Peak Jitter 12.4.2.6 SMB Interface Timings Table 83. Flash Timing Parameters Symbol f SMB Operating Frequency smb T84 t Data Hold Time dhs ...
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Test Port Functionality 13.1 Introduction The 82551QM’s XOR Tree Test Access Port (TAP) is the access point for test data to and from the device. The port provides the ability to perform basic production level testing. 13.2 Test ...
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Networking Silicon 13.2.2 XOR Tree The XOR Tree test mode is the most useful of the asynchronous test modes. It enables the placement of the 82551QM to be validated at board test. The XOR Tree was chosen for ...
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Table 84. XOR Tree Chains (XOR Tree Output) Datasheet Chain Order Chain 1 (FLOE#) 22 PAR 23 AD[16] 24 C/BE#[1] 25 AD[15] 26 AD[14] 27 AD[13] 28 AD[12] 29 AD[11] 30 AD[10] 31 AD[9] 32 AD[8] 33 C/BE#[0] 34 AD[7] ...
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... More information on Intel Handbook. Figure 31. Dimension Diagram for the 196-pin BGA Note: No changes to existing soldering processes are needed for the 0.32 mm substrate change. Datasheet ® device packaging is available in the Intel Packaging 1.56 +/-0.19 0.85 0.40 +/-0.10 0.32 +/-0.04 Note: All dimensions are in millimeters. ...
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Networking Silicon Figure 32. 196 PBGA Package Pad Detail 0.45 Solder Resist Opening 0.60 Metal Diameter As illustrated in Figure is 0.60 mm and the opening in the solder mask is 0.45 mm. The nominal ball sphere diameter ...
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Pinout Information 14.2.1 Pin Assignments Table 85. Pin Assignments Pin A10 SMBCLK A13 SMB_ALERT#/ B10 LAN_PWR_ B13 RBIAS100 C10 C13 D10 D13 E10 E13 ...
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Networking Silicon Table 85. Pin Assignments Pin G10 G13 H10 H13 J10 J13 K10 K13 MDMCS# L10 L13 M1 M4 C/BE#[0] M7 M10 FLA15/EESK M13 N1 ...
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Ball Grid Array Diagram Figure 33. Ball Grid Array Diagram AD[22] AD[21] AD[18] 2 SERR# AD[23] RST# AD[19] 3 VCC VSSPP REQ# AD[20] C/BE#[3] 4 IDSEL AD[24] VSS 5 AD[25] AD[26] CSTSCHG VSS ...
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Networking Silicon 15.0 Reference Schematics This section shows a 10/100 Mbps design using the 82551QM Fast Ethernet Multifunction PCI/ CardBus Controller. 112 Datasheet ...
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A12 C11 B11 TDP C13 TDN C14 E13 RDP E14 RDN Keep all termination resistors as close to the 82551 as ...
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... Pulldown resistors are used on strapped pins to enable the NAND tree test mode to work. The value ohm was chosen strictly on the basis of Intel’s test fixturing requirements Other values can be used, but it is recommended that resistors be used other than hard strapping the pins. F ...