SLXT970AQC.B11-831643 Cortina Systems Inc, SLXT970AQC.B11-831643 Datasheet - Page 11

• Manufacturer Part Number: SLXT970AQC.B11-831643
• Manufacturer: Cortina Systems Inc

Specifications of SLXT970AQC.B11-831643

• Number Of Receivers: 1
• Data Rate: 10/100Mbps
• Operating Supply Voltage (typ): 5V
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Mounting: Surface Mount
• Pin Count: 64
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Lead Free Status / RoHS Status: Not Compliant

Datasheet
1. Pin numbers apply to all package types.
2. I/O Column Coding: I = Input, O = Output, OD = Open Drain, A = Analog.
3. If bit 17.3 = 0, 55Ω series termination resistors are recommended on all output signals to avoid undershoot/overshoot, even
4. The LXT970A Transceiver supports the 802.3 MDIO register set. Specific bits in the registers are referenced using an “X.Y”
on short traces.
If bit 17.3 = 1, termination resistors are not required.
notation, where X is the register number (0-6 or 16-20) and Y is the bit number (0-15).
Table 2.
Pin#
63
62
61
60
59
58
57
56
46
47
48
49
50
51
55
54
64
1
1
MII Signal Descriptions (Sheet 1 of 2)
Pin Name
RX_CLK
TX_CLK
TX_EN
TX_ER
RX_DV
RX_ER
RXD4
RXD3
RXD2
RXD1
RXD0
TXD4
TXD3
TXD2
TXD1
TXD0
COL
CRS
I/O
I/O
O
O
O
O
O
O
I
I
I
2,3
Transmit Data. The Media Access Controller (MAC) drives data to the
LXT970A Transceiver using these inputs. TXD4 is monitored only in Symbol
(5B) Mode. These signals must be synchronized to the TX_CLK.
Transmit Enable. The MAC asserts this signal when it drives valid data on the
TXD inputs. This signal must be synchronized to the TX_CLK.
Transmit Clock. Normally the LXT970A Transceiver drives TX_CLK; in Slave
Clock Mode, TX_CLK is an input. Refer to the Clock Requirements discussion in
the Functional Description section on
25 MHz for 100 Mbps operation.
2.5 MHz for 10 Mbps operation.
Transmit Coding Error. The MAC asserts this input when an error has
occurred in the transmit data stream. When the LXT970A Transceiver is
operating at 100 Mbps, the LXT970A Transceiver responds by sending invalid
code symbols on the line.
Receive Data. The LXT970A Transceiver drives received data on these
outputs, synchronous to RX_CLK.
RXD4 is driven only in Symbol (5B) Mode.
Receive Data Valid. The LXT970A Transceiver asserts this signal when it
drives valid data on RXD. This output is synchronous to RX_CLK.
Receive Error. The LXT970A Transceiver asserts this output when it receives
invalid symbols from the network. This signal is synchronous to RX_CLK.
Receive Clock. This continuous clock provides reference for RXD, RX_DV, and
RX_ER signals. Refer to the Clock Requirements discussion in the Functional
Description section.
25 MHz for 100 Mbps operation.
2.5 MHz for 10 Mbps operation.
Collision Detected. The LXT970A Transceiver asserts this output when
detecting a collision. This output remains High for the duration of the collision.
This signal is asynchronous and inactive during full-duplex operation.
Carrier Sense. During half-duplex operation (bit 0.8 = 0), the
LXT970A Transceiver asserts this output when either transmit or receive
medium is non-idle. During full-duplex operation (bit 0.8 = 1) or repeater
operation
(bit 19.13 = 1), CRS is asserted only when the receive medium is non-idle.
MII Data Interface Pins
Intel
®
LXT970A Dual-Speed Fast Ethernet Transceiver
Signal Description
page
18.
4
11