SLXT970AQC.B11-831643 Cortina Systems Inc, SLXT970AQC.B11-831643 Datasheet - Page 12

• Manufacturer Part Number: SLXT970AQC.B11-831643
• Manufacturer: Cortina Systems Inc

Specifications of SLXT970AQC.B11-831643

• Number Of Receivers: 1
• Data Rate: 10/100Mbps
• Operating Supply Voltage (typ): 5V
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Mounting: Surface Mount
• Pin Count: 64
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Lead Free Status / RoHS Status: Not Compliant

Intel
12
1. Pin numbers apply to all package types.
2. I/O Column Coding: I = Input, O = Output, OD = Open Drain, A = Analog.
3. If bit 17.3 = 0, 55Ω series termination resistors are recommended on all output signals to avoid undershoot/overshoot, even
4. The LXT970A Transceiver supports the 802.3 MDIO register set. Specific bits in the registers are referenced using an “X.Y”
1. Pin numbers apply to all package types.
2. I/O Column Coding: I = Input, O = Output, OD = Open Drain, A = Analog.
Pin#
17
18
27
28
on short traces.
If bit 17.3 = 1, termination resistors are not required.
notation, where X is the register number (0-6 or 16-20) and Y is the bit number (0-15).
Table 2.
Table 3.
®
Pin#
1
LXT970A Dual-Speed Fast Ethernet Transceiver
15
45
44
3
2
1
Pin Name
FIBOP
FIBON
FIBIN
FIBIP
MII Signal Descriptions (Continued) (Sheet 2 of 2)
Fiber Interface Signal Descriptions
FDS/MDINT
Pin Name
TRSTE
MDDIS
MDIO
MDC
I/O
O
I
2
Fiber Output, Positive and Negative. Differential pseudo-ECL driver pair compatible with
standard fiber transceiver for 100BASE-FX.
Fiber Input, Positive and Negative. Differential pseudo-ECL receive pair compatible with
standard fiber transceiver for 100BASE-FX.
I/O
OD
I/O
I
I
I
2,3
Tri-state. In DTE Mode (19.13 = 0), when TRSTE input is High, the
LXT970A Transceiver isolates itself from the MII Data Interface, and controls the
MDIO register bit 0.10 (Isolate bit).
When MDDIS is High, TRSTE provides continuous control over bit 0.10. When
MDDIS is Low, TRSTE sets initial (default) values only and reverts control back
to the MDIO interface.
In Repeater Mode (19.13 = 1), when TRSTE input is High, the
LXT970A Transceiver tri-states the receive outputs of the MII (RXD<4:0>,
RX_DV, RX_ER, RX_CLK).
Management Disable. When MDDIS is High, the MDIO is restricted to Read
Only and the MF<4:0>, CFG<1:0>, and FDE pins provide continual control of
their respective bits. When MDDIS is Low at power up or Reset, the MF<4:0>,
CFG<1:0>, and FDE pins control only the initial or “default” values of their
respective register bits. After the power-up/reset cycle is complete, bit control
reverts to the MDIO serial channel.
Management Data Clock. Clock for the MDIO serial data channel. Maximum
frequency is 2.5 MHz.
Management Data Input/Output. Bidirectional serial data channel for PHY/
STA communication.
Full-Duplex Status. When bit 17.1 = 0 (default), this pin indicates full-duplex
status. (High = full-duplex, Low = half-duplex)
This pin can drive a high efficiency LED. (See
Management Data Interrupt. When bit 17.1 = 1, an active Low output on this
pin indicates status change.
Interrupt is cleared by sequentially reading Register 1, then Register 18.
MII Control Interface Pins
Signal Description
Signal Description
Table 23
4
for detail specifications).
Datasheet