SLXT970AQC.B11-831643 Cortina Systems Inc, SLXT970AQC.B11-831643 Datasheet - Page 21

• Manufacturer Part Number: SLXT970AQC.B11-831643
• Manufacturer: Cortina Systems Inc

Specifications of SLXT970AQC.B11-831643

• Number Of Receivers: 1
• Data Rate: 10/100Mbps
• Operating Supply Voltage (typ): 5V
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Mounting: Surface Mount
• Pin Count: 64
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Lead Free Status / RoHS Status: Not Compliant

2.2.3.2
Datasheet
Figure 5. MII Data Interface
MII Data Interface
Figure 5
transmitting data from the MAC to the LXT970A Transceiver (TXD), and for receiving data
(RXD) from the line.
Each channel has its own clock, data bus and control signals. The LXT970A Transceiver supplies
both clock signals as well as separate outputs for carrier sense and collision.
Normal data transmission across the MII is implemented in 4-bit wide nibbles known as 4B Nibble
Mode. In 5B Symbol Mode, a fifth bit allows 5-bit symbols to be sent across the MII. Refer to the
100 Mbps Operation section on
Transmit Clock
The transmit clock (TX_CLK) is normally generated by the LXT970A Transceiver from the master
25 MHz reference source at the XI input. However, when the XI input is grounded, TX_CLK
becomes the master reference clock input.
The transmit data and control signals must always be synchronized to TX_CLK by the MAC. The
LXT970A Transceiver normally samples these signals on the rising edge of TX_CLK. However,
Advanced TX_CLK Mode is available by setting MII register bit 19.5=1. In this mode, the
LXT970A Transceiver samples the transmit data and control signals on the falling edge of
TX_CLK.
Further details of clock modes can be found in the Operating Requirements section on
Receive Clock
The source of the receive clock varies depending on operating conditions. For 100BASE-TX and
100BASE-FX links, receive clock is continuously recovered from the line. If the link goes down,
and auto-negotiation is disabled, receive clock operates off the master input clock (XI or
TX_CLK).
For 10T links, receive clock is recovered from the line while carrier is active and operates from the
master input clock when the line is idle.
L X T 9 7 0 A
shows the data portion of the MII interface. Separate channels are provided for
R X _ C L K
R X _ D V
R X D < 3 :0 >
R X _ E R
T X _ C L K
T X _ E N
T X D < 3 :0 >
T X _ E R
C R S
C O L
page 32
Intel
M e d ia A c c e s s
®
for additional information.
C o n tro lle r
LXT970A Dual-Speed Fast Ethernet Transceiver
M A C
page
27.
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