SLXT970AQC.B11-831643 Cortina Systems Inc, SLXT970AQC.B11-831643 Datasheet - Page 22

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SLXT970AQC.B11-831643

Manufacturer Part Number
SLXT970AQC.B11-831643
Description
Manufacturer
Cortina Systems Inc
Datasheet

Specifications of SLXT970AQC.B11-831643

Number Of Receivers
1
Data Rate
10/100Mbps
Operating Supply Voltage (typ)
5V
Operating Temperature Classification
Commercial
Operating Supply Voltage (max)
5.25V
Operating Supply Voltage (min)
4.75V
Mounting
Surface Mount
Pin Count
64
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Lead Free Status / RoHS Status
Not Compliant
Intel
22
®
LXT970A Dual-Speed Fast Ethernet Transceiver
The LXT970A Transceiver synchronizes the receive data and control signals to RX_CLK. The
LXT970A Transceiver always changes these signals on the falling edge of RX_CLK in order to
stabilize the signals at the rising edge of the clock with 10 ns setup and hold times.
Transmit Enable
The MAC must assert TX_EN the same time as the first nibble of preamble, and de-assert TX_EN
after the last bit of the packet.
Receive Data Valid
The LXT970A Transceiver asserts RX_DV when it receives a valid packet. Timing changes
depend on line operating speed and MII mode:
Error Signals
In 100TX mode, when the LXT970A Transceiver receives an errored symbol from the network, it
asserts RX_ER and drives “1110” (4B) or “01110” (5B) on the RXD pins.
When the MAC asserts TX_ER, the LXT970A Transceiver drives “H” symbols out on the line.
There are no error functions in 10T mode.
Carrier Sense
Carrier sense (CRS) is an asynchronous output. It is always generated when a packet is received
from the line and in some modes when a packet is transmitted.
On transmit CRS is asserted on a 10BT, half-duplex link when MII Register 19.11 = 0 (default
state), or on any 100 Mbps half-duplex link. Carrier sense is not generated on transmit when the
link operation is full-duplex, or with 10BT half-duplex links when 19.11=1.
Usage of CRS for Interframe Gap (IFG) timing is not recommended for the following reasons:
Operational Loopback
Operational loopback is provided for 10 Mbps half-duplex links when bit 19.11 = 0. Data
transmitted by the MAC will be looped back on the receive side of the MII. Operational loopback
is not provided for 100 Mbps links, full-duplex links, or when 19.11 = 1.
For 100TX and 100FX links with the MII in 4B mode, RX_DV is asserted from the first nibble
of preamble to the last nibble of the data packet.
For 100TX and 100FX links with the MII in 5B mode, RX_DV is asserted starting with the /K
symbol and ending with the /T symbol.
For 10BT links, the entire preamble is truncated. RX_DV is asserted with the first nibble of
the SFD “5D” and remains asserted until the end of the packet.
De-assertion time for CRS is slightly longer than assertion time. This causes the IFG interval
to appear somewhat shorter to the MAC than it actually is on the wire.
CRS de-assertion is not aligned with TX_EN de-assertion on transmit loopbacks in half-
duplex mode.
Datasheet

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