SLXT970AQC.B11-831643 Cortina Systems Inc, SLXT970AQC.B11-831643 Datasheet - Page 5

• Manufacturer Part Number: SLXT970AQC.B11-831643
• Manufacturer: Cortina Systems Inc

Specifications of SLXT970AQC.B11-831643

• Number Of Receivers: 1
• Data Rate: 10/100Mbps
• Operating Supply Voltage (typ): 5V
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Mounting: Surface Mount
• Pin Count: 64
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Lead Free Status / RoHS Status: Not Compliant

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Block Diagram ....................................................................................................... 9
Pin Assignments .................................................................................................10
Network Interface Card (NIC) Application .......................................................... 18
MII Interface ....................................................................................................... 20
MII Data Interface ............................................................................................... 21
Loopback Paths .................................................................................................. 23
Repeater Block Diagram .................................................................................... 24
MDIO Interrupt Signaling .................................................................................... 25
Management Interface - Read Frame Structure ................................................. 25
Management Interface - Write Frame Structure ................................................. 26
Initialization Sequence ....................................................................................... 30
Auto-Negotiation Operation ................................................................................ 31
100BASE-TX Frame Structure ........................................................................... 33
100BASE-TX Data Flow .....................................................................................33
Protocol Sublayers ............................................................................................. 36
100BASE-TX Reception with No Errors ............................................................. 37
00BASE-TX Reception with Invalid Symbol ....................................................... 37
00BASE-TX Transmission with No Errors .......................................................... 37
00BASE-TX Transmission with Collision ............................................................ 37
Voltage Divider ................................................................................................... 45
Typical Interface Circuitry ................................................................................... 46
MII - 100BASE-TX Receive Timing / 4B Mode ................................................... 51
MII - 100BASE-TX Transmit Timing / 4B Mode ................................................. 52
MII - 100BASE-TX Receive Timing / 5B Mode ................................................... 53
100BASE-TX Transmit Timing / 5B Mode .......................................................... 54
MII - 100BASE-FX Receive Timing / 4B Mode ................................................... 55
MII - 100BASE-FX Transmit Timing / 4B Mode .................................................. 56
MII - 10BASE-T Receiving Timing ...................................................................... 57
MII - 10BASE-T Transmit Timing .......................................................................58
10BASE-T SQE (Heartbeat) Timing ................................................................... 59
10BASE-T Jab and Unjab Timing ...................................................................... 59
Auto Negotiation and Fast Link Pulse Timing ....................................................60
Fast Link Pulse Timing ....................................................................................... 60
MDIO Timing when Sourced by STA ................................................................. 61
MDIO Timing when Sourced by PHY ................................................................. 61
Power-Down Recovery Timing (Over Recommended Range) ........................... 62
PHY Identifier Bit Mapping ................................................................................. 66
64-Pin QFP Package Diagram ........................................................................... 73
64-Pin TQFP Package Diagram .........................................................................74
Sample TQFP Package – Intel
Sample Pb-Free (RoHS-Compliant) TQFP Package – Intel
Transceiver75
Sample PQFP Package – Intel
Sample Pb-Free (RoHS-Compliant) PQFP Package – Intel
Transceiver76
Ordering Information Matrix – Sample ................................................................ 78
Intel
®
LXT970A Dual-Speed Fast Ethernet Transceiver
®
®
FALXT970ATC Transceiver............................. 75
SLXT970AQC Transceiver .............................. 76
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®
JALXT970ATC
EGLXT970AQC
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