HY82563EB Intel, HY82563EB Datasheet
HY82563EB
Specifications of HY82563EB
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HY82563EB Summary of contents
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... Substances (RoHS) -banned materials, is available at: ftp://download.intel.com/design/packtech/material_content_IC_Pack In addition, this device has been tested and conforms to the same parametric specifications as previous versions of the device. For more information regarding lead-free products from Intel Corporation, contact your Intel Field Sales representative. Datasheet — Allows PHY placement proximity to I/O back panel ...
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... RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems nuclear facility applications. Intel may make changes to specifications and product descriptions at any time, without notice. ...
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... Block Diagrams .................................................................................................................. 3 3.0 Signal Descriptions............................................................................................................. 5 3.1 Signal Type Definitions.......................................................................................... 5 3.2 Shared PHY Pins .................................................................................................. 6 3.3 MDIO Interface ...................................................................................................... 6 3.4 Port A PHY Interface ............................................................................................. 7 3.5 Port A Kumeran Interface...................................................................................... 8 3.6 Port A LEDs........................................................................................................... 8 3.7 Reset, Power Down, and Initialization Signals ...................................................... 9 3.8 JTAG and IEEE Interface ...................................................................................... 9 3.9 Reserved Signals ................................................................................................10 3 ...
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... JTAG Signals ........................................................................................................ 9 8 Test Signals ........................................................................................................ 10 9 Voltage Control Pins ........................................................................................... 10 10 Clock Generator Related Signals........................................................................ 11 11 Power/Ground Pins ............................................................................................. 11 12 Port B PHY Interface Pins................................................................................... 13 13 Port B Kumeran Interface Pins............................................................................ 14 14 Port B LEDs ........................................................................................................ 15 15 Absolute Maximum Ratings ............................................................................... 17 16 Recommended Operating Conditions ................................................................. and AC Characteristics ................................................................................. ...
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Gigabit Platform LAN Connect Networking Silicon 28 Kumeran (Serial) Receive Specifications ............................................................28 29 Kumeran (Serial) Electrical Idle Detection...........................................................30 30 Kumeran (Serial) Electrical Idle Output ...............................................................30 31 Crystal Parameters..............................................................................................31 32 Specification for External Clock Oscillator...........................................................32 33 Reset Specification..............................................................................................33 34 Power ...
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... Gigabit Platform LAN Connect Networking Silicon 1.0 Introduction The Intel® 82563EB Gigabit Platform LAN Connect is a dual, compact Physical Layer Transceiver (PHY) component designed for 10/100/1000 Mb/s operation. This device uses the Kumeran interface port of the 631xESB/632xESB I/O Controller Hub enabling the routing of long distances inches (~711 mm). The 82564EB Gigabit Platform LAN Connect is the single port implementation. The Intel® ...
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... Table 1. Product Ordering Codes Device Dual Port (Leaded) Single Port (Leaded) Dual Port (Lead Free) Single Port (Lead Free) 2 lists the product ordering codes for the 82563EB dual port device and the Product Code HU82563EB HU82564EB HY82563EB HY82564EB ...
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... SERIAL RX TX Figure 1. 82563EB Dual Port Block Diagram 631xESB/ 632xESB TX RX SERIAL RX TX Figure 2. 82564EB Single Port Block Diagram Port A KUMERAN PHY 82563EB Port B KUMERAN PHY 82564EB Port A KUMERAN PHY TX LINK CAT 5 PARTNER RX TX LINK CAT 5 PARTNER RX TX LINK CAT 5 PARTNER RX 3 ...
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Gigabit Platform LAN Connect Networking Silicon 3.0 Signal Descriptions 3.1 Signal Type Definitions The signals of 82563EB/82564EB are defined as follows: • I: Standard input-only signal • I (T): Functional input signal implemented as a bidirectional for test • ...
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... Bi-directional data signal of the management data interface. 76 TTL6 PU This pin has an internal pull-up. This signal can be left disconnected (or pulled up) if not used. Bits 4:1 of MDIO address These bits are latched at the assertion of PHY_PWR_GOOD or the de-assertion of PHY_RESET_N or PHY_SLEEP. They set the MDIO address as follows: 78 • bit 1 = MDIO_ADD[ (T) TTL • ...
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... BI_DD+/- and in MDIX configuration MDI[3]+/- A A corresponds to BI_DC+/-. 100BASE-TX:Unused. 10BASE-T: Unused. PHY A Link Indication This signal is registered at the rising edge of PHY_PWR_GOOD, I/O TTL8 and is used to determine the clock speed used for PHY_CLK_OUT. Once PHY_PWR_GOOD is 1, LINK_A will always be an output and indicate link up. Description 7 ...
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... O TTL12 This LED will light when the port 0’s PHY transmits a packet LED 6 – Receive Activity LED This LED will light when the port 0’s PHY receives a packet 66 O TTL12 This pin also functions as the clock view pin and will output clock signals required for IEEE conformance testing ...
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... I TTL logic. Needs an external pull-up resistor if the signal isn’t continuously being driven from an external source. Sleep / Power Down This will power down the PHY and the Kumeran of both ports (T) TTL Needs an external pull-down resistor, if the signal isn’t continuously being driven from an external source. ...
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Gigabit Platform LAN Connect Networking Silicon 3.9 Reserved Signals Table 8. Test Signals Signal Name Pin RESERVED_NC RESERVED_PD 82 3.10 Voltage Control Pins Table ...
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... Gigabit Platform LAN Connect Networking Silicon 3.11 Clock Generator Interface Table 10. Clock Generator Related Signals Signal Name Pin XTAL1 21 XTAL2 20 PHY_CLK_OUT 96 3.12 Power/Ground Pins Table 11. Power/Ground Pins (Sheet Signal Name Central VSS Pad VSS VDDO Sub- Type Type 25 MHz Clock/Crystal Input 25 MHz +/- 50 ppm input ...
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... Gigabit Platform LAN Connect Networking Silicon Table 11. Power/Ground Pins (Sheet Signal Name DVDD AVDD AVDDF 92 24 AVDDR 51 12 Sub- Pin Type Type P P 1.2V Digital Power P P 1.9V Analog Power for PHY P P 1.9V Analog Power for Kumeran P P 3.3V Analog Power for Voltage Regulators Description ...
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... Gigabit Platform LAN Connect Networking Silicon 3.13 Port B PHY Interface Note: Port B on the 82563EB dual port device corresponds to connection to Port 1 on the 631xESB/ 632xESB. There is no port B on the 82564EB. Table 12. Port B PHY Interface Pins (Sheet Signal Name Pin MDIB_PLUS[0] 48 ...
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... Gigabit Platform LAN Connect Networking Silicon Table 12. Port B PHY Interface Pins (Sheet Signal Name Pin MDIB_PLUS[2] 42 MDIB_MINUS[2] 41 MDIB_PLUS[3] 39 MDIB_MINUS[3] 38 LINK_B 54 3.14 Port B Kumeran Interface Table 13. Port B Kumeran Interface Pins Signal Name Pin TXB_PLUS 88 TXB_MINUS 87 RXB_PLUS 85 RXB_MINUS 84 14 Sub- Type Description ...
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... O TTL12 This LED will light when port 1’s PHY transmits a packet LED 6 – Receive Activity LED This LED will light when port 1’s PHY receives a packet This pin also functions as the clock 55 O TTL12 view pin and will output clock signals required for IEEE conformance testing ...
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Gigabit Platform LAN Connect Networking Silicon 4.0 Voltage, Temperature and Timing Specifications 4.1 Absolute Maximum Ratings Table 15. Absolute Maximum Ratings Symbol STG a. Maximum ratings are referenced to ground (VSS). Permanent ...
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Gigabit Platform LAN Connect Networking Silicon Table 17. DC and AC Characteristics (Sheet Symbol Output current LOW I OL 12mA drivers (TTL12) Output current HIGH I OH 12mA drivers (TTL12 Inputs with pull-down resistors ...
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Gigabit Platform LAN Connect Networking Silicon Table 18. 3.3V External Power Supply Parameters Title Rise Time Monotonicity Ramp rate at any given time between Slope Operational Range Ripple Overshoot Overshoot Settling (At that time delta voltage should be Time ...
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Gigabit Platform LAN Connect Networking Silicon Table 20. 1.2V External Power Supply Parameters Title Rise Time Monotonicity Slope Operational Range Ripple Overshoot Overshoot Duration Decoupling Capacitance Capacitance ESR a. The peak to peak output ripple is measured at 20 ...
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Gigabit Platform LAN Connect Networking Silicon V Figure 3. 82563EB/82564EB power up sequencing with external regulators 4.4.2.2 External LVR Power down Sequencing There are no specific power down sequencing and tracking requirements for the 82563EB/ 82564EB silicon. The risk ...
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Gigabit Platform LAN Connect Networking Silicon Table 21. 3.3V External Power Supply Parameters Title Ripple Overshoot Overshoot Settling Time a. The peak to peak output ripple is measured at 20 MHz Bandwidth within the operational range. 4.4.4 Internal LVR ...
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Gigabit Platform LAN Connect Networking Silicon V Figure 4. 82563EB/82564EB power up sequencing with internal regulators 4.4.4.2 Internal LVR Power down Sequencing There are no specific power down sequencing and tracking requirements for the 82563EB/ 82564EB device. The risk ...
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Gigabit Platform LAN Connect Networking Silicon 4.4.4.4 1.9V Internal LVR Specification Table 23. 1.9V Internal LVR Specification Parameter Input Voltage Input Capacitance Input Capacitance ESR Load Current Output Voltage Tolerance Output Capacitance Output Capacitance ESR Current Consumption during power ...
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Gigabit Platform LAN Connect Networking Silicon Table 24. 1.2V Internal LVR Specification (Sheet Parameter Output Voltage Tolerance Output Capacitance Output Capacitance ESR Current Consumption during power up Current Consumption during power down Peak to Peak output ...
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Gigabit Platform LAN Connect Networking Silicon The effective resistance of the pass resistors should be approximately 0.5 power dissipation rating of 0.5 Watts for the 82563EB. implementation. CTRL_18 Note: PNP needs 0.5 inch by 0.5 inch thermal relief pad ...
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... The Kumeran interface is electrically compatible with the SERDES implemented in 1000Base-BX applications, as defined in the PICMG 3.1 Specification, Version 1.0, Chapter 5, Backplane Physical Layers Interfaces. It also implements electrical idle as described in section 3.5.4. As part of the electrical idle implementation, the Kumeran interface also needs to be able to detect when the 631xESB/632xESB is in electrical idle ...
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Gigabit Platform LAN Connect Networking Silicon The differential peak and differential peak to peak voltage is defined as follows: • max (|V DIFFp • (2* V DIFFp-p In addition, the transmitter must meet the following ...
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Gigabit Platform LAN Connect Networking Silicon Table 28. Kumeran (Serial) Receive Specifications Symbol Parameter Common Mode Return TDR Rise Impedance at Connection Note: TDR measurements are recorded times. Record time = TDR transmit time *2. The receiver expects to ...
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Gigabit Platform LAN Connect Networking Silicon 4.6.3.1 Electrical Idle Detection The 82563EB/82564EB detects that the 631xESB/632xESB has gone into electrical idle when it senses that the differential voltage has gone below and is remaining below a threshold voltage. Table ...
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Gigabit Platform LAN Connect Networking Silicon 4.7 Crystal The quartz crystal is strongly recommended as a low cost and high performance choice with the 82563EB/82564EB device. Quartz crystals are the mainstay of frequency control components and are available from ...
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... Frequency Tolerance Operating Temperature Aging 4.8 Reset and Initial Clock Timing PHY_PWR_GOOD must be low throughout the time that the power supplies are ramping. This guarantees that the 82563EB/82564EB resets cleanly. VDDO, AVDDR (3.3V) AVDD, AVDDF (1.9V) PHY _PWR _GOOD PHY _CLK _OUT Figure 10 ...
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... When 0b, the entire chip is held in reset except PHY_CLK_OUT. When 1b the entire chip is powered down, except PHY_CLK_OUT. The port’s PHY and Kumeran can be disabled by writing the “Disable Port” bit of the “Power Management Control” register. ThE 82563EB/82564EB can be powered down with an indication over the Kumeran bus or by writing the “ ...
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... Total Device 145 mW Power Table 36. Power Supply Characteristics - Uninitialized/Disabled D(n) Uninitialized (PHY PWR GOOD = Typ Icc (mA Total Device 116 mW Power a. Equivalent to PHY_SLEEP = 1b and/or PHY_RESET_N = 0b. 34 D0a (Both Ports) 10 Mb/s Operation Max Icc Typ Icc Max Icc (mA) (mA) (mA 140 140 ...
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Gigabit Platform LAN Connect Networking Silicon Table 37. Power Supply Characteristics - Complete Subsystem (Including Magnetics, LED, and Regulator Circuits) 10 Mb/s Operation Typ lcc 3 1 1.2 V 280 Subsystem 3.3 V 1121 mW ...
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... Gigabit Platform LAN Connect Networking Silicon 5.0 Package and Pinout Information This section describes the 82563EB/82564EB device physical characteristics. The pin number-to- signal mapping is indicated beginning with 5.1 Package Information The package used for the 82563EB/82564EB is a 100-pin TQFL with an Exposed-Pad* ...
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Gigabit Platform LAN Connect Networking Silicon Figure 12. Mechanical Specifications and Notes 38 ...
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Gigabit Platform LAN Connect Networking Silicon 5.2 Thermal Specifications The 82563EB/82564EB device is specified for operation when the ambient temperature (T within the range of 0 The maximum junction temperature is 120° C. The maximum ambient temperature with airflow ...
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Gigabit Platform LAN Connect Networking Silicon 5.3 Pinout Information Table 39. 82563EB/82564EB Pinout by Pin Number Order (Sheet Pin 1 JTAG_TDI 2 DVDD 3 JTAG_TMS 4 RESERVED_NC 5 RESERVED_NC 6 RESERVED_NC 7 DVDD 8 RESERVED_NC 9 ...
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... Table 39. 82563EB/82564EB Pinout by Pin Number Order (Sheet 82563EB Pin Dual Port 35 AVDD 36 MDIA_PLUS[3] 37 MDIA_MINUS[3] 38 MDIB_MINUS[3] 39 MDIB_PLUS[3] 40 AVDD 41 MDIB_MINUS[2] 42 MDIB_PLUS[2] 43 MDIB_MINUS[1] 44 MDIB_PLUS[1] 45 AVDD 46 AVDD 47 MDIB_MINUS[0] 48 MDIB_PLUS[0] 49 RESERVED_NC 50 PHY_REF 51 AVDDR 52 RESERVED_NC 53 RESERVED_NC 54 LINK_B 55 LEDB_RX_ACTIVITY 56 LEDB_TX_ACTIVITY 57 LEDB_DUPLEX 58 LEDB_SPEED_1000_N 59 DVDD 60 VDDO 61 LEDB_SPEED_100_N 62 LEDB_ACTIVITY_N 63 LEDB_LINK_UP_N 64 DVDD 65 LINK_A 66 LEDA_RX_ACTIVITY 67 LEDA_TX_ACTIVITY ...
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... TXA_PLUS, 91 TXA_MINUS 92 AVDDF 93 RXA_PLUS, 94 RXA_MINUS 95 TEST_JTAG 96 PHY_CLK_OUT 97 VDDO 98 RESERVED_NC 99 JTAG_TDO 100 JTAG_TCK Central VSS Pad a. The 82564EB device uses the same name as the 82563EB device unless otherwise specified. b. For those external strappings that state KΩ, 5%, the recommended value within that range is 3.3 KΩ ...
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... Voltage Control Kumeran Port B Port B LEDs MDIA_PLUS [3:0] MDIA_MINUS [3:0] PHY A LINK _A PHY _REF XTAL 1 Clocks XTAL 2 PHY _CLK _OUT JTAG _TCK JTAG _TDI JTAG _TDO JTAG JTAG _TMS TEST _JTAG VDDO (3.3V) AVDDR (3.3V ) DVDD (1.2V) AVDD (1.9V) AVDDF (1.9V) ...
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Gigabit Platform LAN Connect Networking Silicon 5.5 Visual Pin Assignments JTAG_TDI 1 DVDD 2 JTAG_TMS 3 RESERVED _NC 4 RESERVED _NC 5 RESERVED _NC 6 DVDD 7 RESERVED _NC 8 RESERVED _NC 9 RESERVED _NC 10 VDDO 11 DVDD ...
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Gigabit Platform LAN Connect Networking Silicon JTAG_TDI 1 DVDD 2 JTAG_TMS 3 RESERVED _NC 4 RESERVED _NC 5 RESERVED _NC 6 DVDD 7 RESERVED _NC 8 RESERVED _NC 9 RESERVED _NC 10 VDDO 11 DVDD 12 RESERVED _NC 13 ...
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