L-FW802B-DB LSI, L-FW802B-DB Datasheet
L-FW802B-DB
Specifications of L-FW802B-DB
Related parts for L-FW802B-DB
L-FW802B-DB Summary of contents
Page 1
... While unpowered and connected to the bus, the device will not drive TPBIAS on a connected port even if receiving incoming bias voltage on that port. Does not require external filter capacitors for PLL. Does not require a separate 5 V supply for 5 V link controller interoperability. ™ Interoperable across 1394 cable with 1394 physi- cal layers (PHY) using 5 V supplies ...
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... Figure 2. Pin Assignments ..........................................................................................................................................6 Figure 3. Typical External Component Connections .................................................................................................11 Figure 4. Typical Port Termination Network ..............................................................................................................12 Figure 5. Crystal Circuitry ..........................................................................................................................................13 Figure 6. Dn, CTLn, and LREQ Input Setup and Hold Times Waveforms ................................................................19 Figure 7. Dn, CTLn Output Delay Relative to SYSCLK Waveforms ......................................................................... 19 Tables Tables 1. Signal Descriptions ......................................................................................................................................7 Tables 2. Absolute Maximum Ratings .......................................................................................................................14 Tables 3 ...
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... TPB cable pair. The received data-strobe information is decoded to recover the receive clock signal and the serial data bits. The serial data bits are split into two (for S100), four (for S200), or eight (for S400) parallel streams, resynchronized to the local system clock, and sent to the associated LLC ...
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... When the C/LKON signal is asserted, it means the node is a contender for bus manager. When the signal is not asserted, it means that the node is not a contender. The C bit corresponds to bit 20 in the self- ID packet. PC[0:2] corresponds to the pwr field of the Self-ID packet in the following manner: PC0 ...
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... CTL0 INTERFACE I/O CTL1 PC0 PC1 PC2 C/LKON /RESET Agere Systems Inc. FW802B Low-Power PHY IEEE 1394A-2000 Two-Cable Transceiver/Arbiter Device RECEIVED DATA VOLTAGE DECODER/ RETIMER CURRENT GENERATOR ARBITRATION AND CONTROL STATE MACHINE LOGIC CABLE PORT 0 CABLE PORT 1 TRANSMIT DATA ENCODER CRYSTAL ...
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... LREQ CTL0 3 CTL1 CNA 15 LPS 16 Note: Active-low signals are indicated by “/” at the beginning of signal names, within this document PIN #1 IDENTIFIER AGERE FW802B Figure 2. Pin Assignments Data Sheet, Rev. 3 May 2004 DDA 42 TPBIAS1 41 TPA1+ 40 TPA1– 39 TPB1+ 38 TPB1– 37 TPBIAS0 36 TPA0+ 35 TPA0– ...
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... CTL1 D[0:7] I/O 9, 10, 11, 12 Active-low signals are indicated by “/” at the beginning of signal names, within this document. Agere Systems Inc. FW802B Low-Power PHY IEEE 1394A-2000 Two-Cable Transceiver/Arbiter Device Name/Description Bus Manager Capable Input and Link-On Output. On hardware reset (/RESET), this pin is used to set the default value of the contender status indicated during self-ID. The bit value programming is done by tying the signal through a 10 kΩ ...
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... LLC pulsed output that is active when the LLC is powered for the purpose of monitoring the LLC power status. If LPS is inactive for more than 1.2 µs and less than 25 µs, the PHY-link interface is reset. If LPS is inactive for greater than 25 µs, the PHY will disable the PHY/link interface to save power ...
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... SYSCLK O 36 TPA0+ Analog I/O Port0, Port Cable Pair A. TPA0± is the port A connection to the twisted- 35 TPA0− 41 TPA1+ Analog I/O Port1, Port Cable Pair A. TPA1± is the port A connection to the twisted- 40 TPA1− 34 TPB0+ Analog I/O Port0, Port Cable Pair B. TPB0± is the port B connection to the twisted- 33 TPB0− ...
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... XO pin (see Figures 3 and 5). For more details, refer to L the Crystal Selection Considerations section in the data sheet. Note that it is very important to place the crystal as close as possible to the XO and XI pins, i.e., within 0.5 in./1.27 cm. Data Sheet, Rev. 3 May 2004 signals should be tied together to a low- Agere Systems Inc ...
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... SS 2 CTL0 3 CTL1 LLC CNA 15 LPS LLC PULSE See Figure 4 for typical port termination network. Figure 3. Typical External Component Connections Agere Systems Inc. Two-Cable Transceiver/Arbiter Device PIN #1 IDENTIFIER AGERE FW802B DDA 43 TPBIAS1 42 TPA1+ 41 TPA1– PORT 1* 40 TPB1+ 39 TPB1– 38 TPBIAS0 37 ...
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... XI and XO terminals to provide the reference for an internal oscillator circuit. The IEEE 1394a-2000 standard requires that FW802B have less than ±100 ppm total variation from the nominal data rate, which is directly influenced by the crystal. To achieve this recommended that an oscillator with a nominal 50 ppm or less frequency tolerance be used. ...
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... Minimizing the loop area minimizes the effect of the resonant current that flows in this resonant circuit. This layout unit (crystal and load capacitors) should then be placed as close as possible to the PHY XI and XO terminals to minimize trace lengths. Vias should not be used to route the XI and XO signals. ...
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... Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso- lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability ...
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... Common-mode Voltage Nonsource Power Mode* Receive Input Jitter Receive Input Skew Between TPA and TPB cable inputs, Between TPA and TPB cable inputs, Between TPA and TPB cable inputs, Positive Arbitration Comparator Input Threshold Voltage Negative Arbitration Comparator Input Threshold Voltage ...
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... Common-mode Speed Signaling Current, TPB+, TPB− * Limits are defined as the algebraic sum of TPA+ and TPA− driver currents. Limits also apply to TPB+ and TPB− as the algebraic sum of driver currents. † Limits are defined as the absolute limit of each of TPB+ and TPB− driver currents. ...
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... Falling Input Threshold Voltage*, LREQ, CTLn, Dn Bus Holding Current, LREQ, CTLn, Dn Rising Input Threshold Voltage LPS Falling Input Threshold Voltage LPS * Device is capable of both differentiated and undifferentiated operation. Agere Systems Inc. FW802B Low-Power PHY IEEE 1394A-2000 Two-Cable Transceiver/Arbiter Device (continued) Test Conditions Symbol ...
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... Fall Time, Transmit (TPA/TPB Setup Time, su Dn, CTLn, LREQ↑↓ to SYSCLK↑ t Hold Time, h Dn, CTLn, LREQ↑↓ from SYSCLK↑ t Delay Time, d SYSCLK↑ to Dn, CTLn↑↓ Table 7. Clock Characteristics Parameter External Clock Source Frequency 18 18 Measured ...
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... Data Sheet, Rev. 3 May 2004 Timing Waveforms Figure 6. Dn, CTLn, and LREQ Input Setup and Hold Times Waveforms Figure 7. Dn, CTLn Output Delay Relative to SYSCLK Waveforms Agere Systems Inc. FW802B Low-Power PHY IEEE 1394A-2000 Two-Cable Transceiver/Arbiter Device SYSCLK tsu Dn, CTLn, LREQ ...
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... REQUIRED The meaning of the register fields within the PHY register map are defined by Table 9 below. Power reset values not specified are resolved by the operation of the PHY state machines subsequent to a power reset. Table 9. PHY Register Fields for the Cable Environment ...
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... Loop Detect. A write of one to this bit clears it to zero. 1 Cable Power Failure Detect. Set to one when the PS bit changes from one to zero. A write of one to this bit clears it to zero. 0 Arbitration State Machine Timeout. A write of one to this bit clears it to zero (see MAX_ARB_STATE_TIME). ...
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... Page_select and the desired port number to Port_select in the PHY register at address 0111 . The format of the port status page is illustrated by Table 10 below; reserved fields are shown shaded. The 2 meanings of the register fields with the port status page are defined by Table 11. ...
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... Data Sheet, Rev. 3 May 2004 Internal Register Configuration The meaning of the register fields with the port status page are defined by Table 11 below. Table 11. PHY Register Port Status Page Fields Field Size Type AStat 2 r BStat 2 r Child 1 r Connected 1 r Bias ...
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... FW802B Low-Power PHY IEEE 1394A-2000 Two-Cable Transceiver/Arbiter Device Internal Register Configuration The vendor identification page is used to identify the PHY’s vendor and compliance level. The page is selected by writing one to Page_select in the PHY register at address 0111 shown in Table 12; reserved fields are shown shaded. ...
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... DETAIL B 0.50 TYP Ordering Information Device Code FW802B-DB 64-Pin TQFP L-FW802B-DB 64-Pin TQFP (lead-free effort to better serve its customers and the environment, Agere is switching to lead-free packaging on this product (no intentional addition of lead). Agere Systems Inc. FW802B Low-Power PHY IEEE 1394A-2000 Two-Cable Transceiver/Arbiter Device ...
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... Tel. (44)1344 296 400 Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. Agere is a registered trademark of Agere Systems, Inc. Agere Systems and the Agere logo are trademarks of Agere Systems Inc. ...