WG82577LM S LGWS Intel, WG82577LM S LGWS Datasheet
WG82577LM S LGWS
Specifications of WG82577LM S LGWS
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WG82577LM S LGWS Summary of contents
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... PMA loopback capable (no echo cancel) ® 1. Refer to the latest Intel 82577 Specification Update for more details. 2. The MAC is incorporated into the Intel® 5 Series Express Chipset. June 2010 Advanced cable diagnostics — TDR — Channel frequency response Extended configuration load sequence ...
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... Intel Corporation (“Intel”). In the event that you do not agree with any of these terms and conditions, do not use or install the Pre-Release Product and promptly return it unused to Intel. ...
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... Overview ................................................................................................ 6 2.4 Transitions between SMBus and PCIe interfaces ...................................................... 8 2.4.1 Switching from SMBus to PCIe ................................................................... 8 2.4.2 Switching from PCIe to SMBus ................................................................... 8 2.5 Intel® 5 Series Express Chipset/82577 – SMBus/PCIe Interconnects.......................... 9 3.0 Pin Interface ........................................................................................................... 11 3.1 Pin Assignment ................................................................................................. 11 3.1.1 Signal Type Definitions............................................................................ 11 3.1.2 PCIe Interface Pins (8)............................................................................ 12 3 ...
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... Basic Configuration Software Words ........................................................ 111 ® 9.4 Intel 5 Series Express Chipset/82577 NVM Contents........................................... 113 ® 10.0 Intel 5 Series Express Chipset MAC Programming Interface................................. 115 10.1 Register Byte Ordering ..................................................................................... 115 10.2 Register Conventions ....................................................................................... 116 10.2.1 PCI Configuration and Status Registers - CSR Space.................................. 117 11 ...
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... Datasheet—82577 GbE PHY 11.6 Mechanical ..................................................................................................... 179 11.7 Oscillator/Crystal Specifications......................................................................... 180 12.0 Schematic and Board Layout Checklists ................................................................. 183 13.0 Reference Schematics ........................................................................................... 185 14.0 Models................................................................................................................... 187 v ...
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... Removed old section 8. • Updated section 10.3.1.11 (bit 12 and 13 desctiptions). • Updated figure 1. • Updated table 2. • Updated section 7.4 and 10.3.1.2 (added Intel • Added power sequencing note to section 5.3.2. February 2010 2.3 • Updated section 6.4.2.2 (added Windows* 7 reference). • ...
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... Updated Figure 1 (removed ferrite beads). • Updated Section 1.2 (added note), 2.2 (added note), 2.3 (added note), and 7.2.2. April 2008 0.7 Added a discrete/integrated magnetics specifications table to Section 7.0. Mar 2008 0.6 Major revision (all sections). Feb 2008 0.5 Initial release (Intel Confidential). vii ...
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... Overview The 82577 is a single port Gigabit Ethernet Physical Layer Transceiver (PHY). It connects to the Intel (MAC) through a dedicated interconnect. The 82577 supports operation at 1000/100/ 10 Mb/s data rates. The PHY circuitry provides a standard IEEE 802.3 Ethernet interface for 1000BASE-T, 100BASE-TX, and 10BASE-T applications (802.3, 802.3u, and 802 ...
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... Introduction—82577 GbE PHY Crystal Testability Power Figure 1. 82577 Block Diagram 1.3 Main Flows The 82577 main interfaces are PCIe and SMBus on the host side and the MDI interface on the link side. Transmit traffic is received from the MAC device through either PCIe or SMBus on the host interconnect and then transmitted on the MDI link ...
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... Intel Corporation ® • Intel 82577 Schematic and Layout Checklists, Intel Corporation ® • Intel 82577 MDI Differential Trace and Power Loss Calculators, Intel Corporation 1.5 Product Codes Table 1 lists the product ordering codes for the 82577 GbE controller. Refer to the ® ...
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... Introduction—82577 GbE PHY 1.6 Product Matrix Method of enabling/disabling features in SKUs Link Speed Platform Gigabit Mobile Note: The 82577 does not support server operating systems such as Windows Server* 2008 and Windows Server* 2003. Performance Segment Description Device ID 82577 for Corporate 10EA ...
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... PCIe Interface Signals The signals used to connect between the MAC and the PHY in this mode are: • Serial differential pair running at 1.25 Gb/s for Rx • Serial differential pair running at 1.25 Gb/s for Tx • 100 MHz differential clock input to the PHY running at 100 MHz • ...
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... Chipset. No other device (like an external BMC) can be connected to SMLink0 when the 82577 is connected to the Intel 2.3.1 Overview SMBus is used as an interface to pass traffic between the 82577 and the Intel Express Chipset when the system low power state (Sx state). The interface is also used to enable the Intel as passing in-band information between them. ...
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... ACKs, NACKs, STARTs, or STOPs) in the SMBus transaction. The polynomial for this CRC-8 is The PEC calculation is reset when any of the following occurs: • A STOP condition is detected on the host SMBus • An SMBus hang is detected on the host SMBus • The SMB_CLK is detected high for ~50 µs 7 82577 GbE PHY—Interconnects ...
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... PE_RST_N signal is high. Switching the communication to SMBus is only needed to enable host wake up in low power states and is controlled by the Intel® 5 Series Express Chipset. The switching from PCIe to SMBus is done when the PE_RST_N signal is low. ...
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... Intel® 5 Series Express Chipset/82577 – SMBus/PCIe Interconnects The 82577 can be connected to any x1 PCIe port in Intel The PCIe port that connects to the 82577 is selected by PCHSTRP9, bits [11:8] in the SPI Flash descriptor region. For more information on this setting, please refer to the ® ...
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... Interconnects—82577 GbE PHY Note: This page intentionally left blank. 10 ...
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... The 82577 is packaged in a 48-pin package with a 0.4 mm lead pitch. There are 48 pins on the periphery and a die pad (Exposed Pad*) for ground. Note: Refer to the reference schematics for pin connection details. Contact your Intel representative for access. 3.1.1 Signal Type Definitions ...
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... K resistor (while in Sx mode). Type Op Mode Name and Function 1 T/s Connect to VCC3P3 through a 5%, 3.01 K resistor. 2 T/s Connect to VCC3P3 through a 5%, 3.01 K resistor. Connect to the LAN_PHY_PWR_CTRL/GPIO12 pin in the ® Intel 5 Series Express Chipset Note: When this pin is set to 0b, the 82577 is disabled ...
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... PHY Pins (14) 3.1.5.1 LEDs (3) This table lists the functionality of the LED output pins. Refer to the Intel Family Platform Design Guide (PDG) for LED connection details. Pin Name Pin # LED0 26 LED1 27 LED2 25 3.1.5.2 Analog Pins (11) Pin Name Pin# MDI_PLUS[0] 13 MDI_MINUS[0] 14 MDI_PLUS[1] ...
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... In Input connected to logic 1b and test mode is enabled. Type Name and Function 1.0 Vdc supply. Power Note: Can also be connected to the Intel® 5 Series Express 46, 47 Chipset Switching Voltage Regulator (SVR). 4 Power Regulator output. Connect to GND through a 1 µF capacitor. Power Connect to GND through a 1 µF capacitor. ...
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... See Exposed Pad Dimensions A1 0.00 See Exposed Pad Dimensions A2 0. 0.24 0.30 O 0.13 R Tolerance Requirement for D1/E1: +/- 0.1 mm 82577 GbE PHY—Package E2 NOTE MAX MIN NOM MAX 4.40 4.20 4.30 4.40 Note NOM MAX 0.85 0.90 0.01 0.05 0.65 0.70 0.20 REF 6 ...
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... Package—82577 GbE PHY 4.2 Package Electrical and Thermal Characteristics The thermal resistance from junction to case, qJC, is 15.1 ×C/Watt. The thermal resistance from junction to ambient, qJA follows: 4-layer PCB, 85 degrees ambient. Air Flow (m/s) No heat sink is required. Maximum 119 1 118 2 116 qJA (× ...
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... X 3.3v 4 3.3v 15, 19 3.3v 29 3.3VDD 5 82577 C7 10 CTRL1p0 7 9 1.0V 37,46,47 1. 1.0V 8,11,16,40 82577 GbE PHY—Package Figure 4 shows a typical Magnetic Center Tap X No Connect 1uf 1uf +3.3V LAN C6 C5 +3.3V LAN BCP69 R3 1.0V can be supplied from the 1.0v ...
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... Package—82577 GbE PHY 4.4 Pinouts (Top View, Pins Down) RSVD_VCC3P3 RSVD_VCC3P3 LAN_DISABLE_N VDD3P3_OUT VDD3P3_IN CTRL_1P0 VDD1P0 XTAL_OUT XTAL_IN VDD1P0 Figure 5. 82577 Pinouts Pin 82577 5 48 Pin QFN 6 VCT 0.4 mm pin pitch with Exposed Pad RBIAS Pin 49 - VSS_EPAD PE_RST_N 35 JTAG_TCK 34 JTAG_TDO ...
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... MDI_PLUS[2] 9 MDI_MINUS[2] 10 VDD1P0 11 MDI_PLUS[3] 12 MDI_MINUS[3] 25 VDD1P0 26 PETp 27 PETn 28 VDD1P0 29 PERp 30 PERn 31 VDD1P0 32 PE_CLKP 33 PE_CLKN 34 VDD1P0 35 VDD1P0 36 CLK_REQ_N 49 82577 GbE PHY—Package Side Pin Number Bottom 13 Bottom 14 Bottom 15 Bottom 16 Bottom 17 Bottom 18 Bottom 19 Bottom 20 Bottom 21 Bottom 22 Bottom 23 Bottom 24 Top 37 Top 38 Top 39 Top 40 Top ...
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... Package—82577 GbE PHY Note: This page intentionally left blank. 20 ...
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... Start PCIe training Send link status message PHY starts link auto-negotiation 82577 GbE PHY—Initialization Internal Xosc stabilizes Internal power on reset is de-asserted ® Wait for Intel 5 Series Express Chipset SMBus address valid MDIO registers are initialized by the MAC PHY establishes link ...
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... Platform power ramps up (3.3 V dc/1.0 Vdc) 2 XTAL is stable after T 3 Internal Power On Reset triggers T 4 PCIe training if PE reset is de-asserted. 5 Wait for Intel 6 Send Link Status message. 7 MAC configures the 82577. 8 PHY goes through auto-negotiation to acquire link. sec. XTAL after XTAL is stable. Strapping options are latched. ...
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... Reset 1. Asserting a 3.3 Vdc power on reset should move the PHY out of power down mode. 2. PHY registers (page 0 in MDIO space and any aliases to page 0) are reset during a PHY soft reset. The rest of the 82577’s MDIO space is not reset. 23 Non-PHY ...
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... Timing Guarantees The 82577 guarantees the following start-up and power state transition related timing parameters. Note: For platform power sequencing requirements for the Intel® 5 Series Express Chipset MAC, refer to the Intel® 5 Series Express Chipset EDS. Table 6. Timing Guarantees Parameter ...
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... This section describes how power management is implemented in the 82577. 6.1 Power Targets Table 7 lists the targets for device power for the 82577. Note that power is reduced according to link speed and link activity. Note: Device power is the power dissipated by the 82577. 25 82577 GbE PHY—Power Management and Delivery ...
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... Measured power could be higher or lower based on measurement setup and PHY power delivery configuration. 2. SVR efficiency is assumed to be 80%. 3. Assumes the system is in the Moff state and SLP_LAN# is used to gate PHY power. 1 Solution Power 1.05 [mW] - Shared 3.3 Vdc Device Vdc Intel® 5 Series Current Power Current Express [mA] (mW) [mA] Chipset SVR 2 ...
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... The 1.0 Vdc rail can be supplied in one of two ways (see • An external power supply not dependent on support from the 82577. For example, ® the Intel 5 Series Express Chipset 1.05 Vdc SVR can be tied to the 1.0 Vdc PHY supply. • A discrete LVR solution, where the base current of PNP power transistor is driven by the 82577, while the power transistor is placed externally ...
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... The 82577 signals the MAC that link energy was detected by clearing the Cable Disconnect bit in the PCIe or SMBus interface. • The PHY waits until the auto-negotiation break link timer expires (T then starts to advertise data on the line. 6.3.1.3 Power Down State The 82577 enters a power-down state when the LAN_DISABLE_N pin is set to zero ...
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... Intel Auto Connect Battery Saver (ACBS) ® Intel Auto Connect Battery Saver for the 82577 is a hardware-only feature that automatically reduces the PHY to a lower power state when the power cable is disconnected. When the power cable is reconnected, it renegotiates the line speed following IEEE specifications for auto negotiation ...
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... Then, with both the monitor off and the network idle, the LAN negotiates to the lowest possible link speed supported by both the PHY and the link partner (typically 10 Mb/s). If the link partner is hard-set to only advertise a certain speed, then the LAN negotiates to the advertised speed ...
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... For example, if the 82577 advertises 10 Mb/s only and the link partner supports 1000/100 Mb/s only, a 100 Mb/s link is established. LPLU is controlled through the LPLU bit in the PHY Power Management register. The MAC sets and clears the bit according to hardware/software settings. The 82577 auto negotiates with the updated LPLU setting on the following auto-negotiation operation ...
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... LAN Disable Recommendations LAN_DISABLE_N needs to be connected to the GPIO12/LAN_PHY_PWR_CTRL output of ® the Intel 5 Series Express Chipset. GPIO12 also needs to be configured using Intel Series Express Chipset soft straps as LAN_PHY_PWR_CTRL (bit [20] of PCHSTRP0 register - LAN_PHY_PWR_CTRL/GPIO12. Refer to the Intel Family External Design Specification (Intel ® ...
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... The implementation of asymmetric flow control allows for one link partner to send flow control packets while being allowed to ignore their reception. For example, not required to respond to PAUSE frames. 33 82577 GbE PHY—Device Functionality ...
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... Device Functionality—82577 GbE PHY 7.3.1 MAC Control Frames and Reception of Flow Control Packets Three comparisons are used to determine the validity of a flow control frame match on the six-byte multicast address for MAC control frames or to the station address of the device (Receive Address Register 0). ...
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... Wake Up The 82577 supports host wake up. This mechanism uses in-band messages to wake the Intel from a sleep state. The host can enable host wake up from the 82577 by setting the Host_WU_Active bit. When this bit is set, after the host transitions to a low power state, the SMBus interface is still active and the wake up indication from the 82577 to ® ...
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... Note: Once wake up is enabled, the 82577 stops responding to SMBus commands. Host wake up: 1. When a WoL packet/event is detected, the 82577 sends an in-band message to the Intel® 5 Series Express Chipset indicating a host wake up. ® 2. The Intel 5 Series Express Chipset wakes the host. ...
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... PM_PME message (if configured to). At power up, if the 82577’s wake up functionality is enabled, the APM Enable bits from the NVM are written to the 82577 by the Intel Enable (APME) bits of the Wakeup Control (WUC) register. These bits control the enabling of APM wake up. ...
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... If a packet passes both the standard address filtering and at least one of the enabled wake up filters, the 82577: • Initiates a the Intel • Sets one or more of the Received bits in the WUS register. Note that more than one bit is set if a packet matches more than one filter. ...
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... Offset # of Bytes Field Value Action Destination Address Compare Field Value Destination Address Field Destination Address 82577 GbE PHY—Device Functionality Comment Match any pre-programmed address as defined in the receive address Action Comment Compare See previous paragraph. Value Action Comment FF*6 Compare ...
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... Device Functionality—82577 GbE PHY 7.4.1.3.1.4 Magic Packet Magic packets are defined as follows: — Magic Packet Technology Details - Once the 82577 has been put into Magic Packet mode, it scans all incoming frames addressed to the node for a specific data sequence, which indicates to the MAC that this is a Magic Packet frame. A ...
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... Protocol Address Length 0x04 Compare Operation 0x0001 Compare Sender Hardware Address - Ignore Sender IP Address - Ignore Target Hardware Address - Ignore Target IP Address IP4AT Compare 82577 GbE PHY—Device Functionality Comment MAC Header – processed by main address filter Might match any of four values in IP4AT ...
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... Device Functionality—82577 GbE PHY 7.4.1.3.1.6 Directed IPv4 Packet The 82577 supports receiving Directed IPv4 packets for wake up if the IPV4 bit (bit 6) is set in the WUFC register. Three IPv4 addresses are supported, which are programmed in the IPv4 Address Table (IP4AT). A successfully matched packet must contain the station’ ...
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... Compare Field Value Destination Address Source Address Possible VLAN Tag Possible Len/LLC/SNAP Header Type 0x8137 Some IPX Information - IPX Diagnostic Socket 0x0456 82577 GbE PHY—Device Functionality Comment Match value in IP6AT Action Comment Compare Skip Skip Skip Compare IPX Ignore Compare ...
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... After the page is set to the wake up page, the Address field is no longer translated as reg_addr (register address) but as an instruction. If the given address is in [0..15] range meaning PHY registers, the functionality remains unchanged. There are two valid instructions: Instruction ...
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... PHY loopback is supported in the 82577. Software or firmware should set the 82577 to the loopback mode (via the MDIC register) writing to the PHY Loopback Control register (address 19). The MAC must be in forced link and in full duplex mode for PHY loopback to operate. The following bits must be configured to enable PHY loopback: CTRL ...
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... Device Functionality—82577 GbE PHY Note: This page intentionally left blank. 46 ...
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... When a register number is used for registers 16-21, or 23-28, it refers to the register in page 0. — Register 31 in PHY address 01, is the page register itself and doesn’t belong to any page always written as register 31. • By page and register number — This can be written out as page x, register y, but is often abbreviated x.y • ...
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... PHY address 01, are divided into pages. Each page has 32 registers. Registers 0-15 are identical in all the pages and are the IEEE defined registers. Register 31 is the page register in all pages of PHY address 01. All other registers are page specific. In order to read or write a register, software should define the appropriate PHY address ...
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... GbE PHY—Programmer’s Visible State Register Name 0 Control 1 Status 2 PHY Identifier 1 3 PHY Identifier 2 4 Auto-Negotiation Advertisement 5 Auto-Negotiation Link Partner Ability 6 Auto-Negotiation Expansion 7 Auto-Negotiation Next Page Transmit 8 Link Partner Next Page ...
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... Programmer’s Visible State—82577 GbE PHY Table 9. Address Map 01 778 01 778 01 778 01 778 01 770 01 770 01 770 01 770 01 770 01 770 01 776 800 01 800 01 800 01 800 01 800 01 800 01 800 01 800 01 800 01 800 01 800 01 800 01 800 01 800 01 800 01 800 01 800 01 800 01 800 Late Collision Count ...
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... When this bit is cleared, the link configuration is determined manually. R Enables auto-negotiation process Disables auto-negotiation process Power down. R Normal operation. Setting this bit isolates the PHY from the MII or GMII interfaces. R Isolates the PHY from MII Normal operation Restarts auto-negotiation process. R/W, Normal operation. ...
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... Auto-negotiation process complete Auto-negotiation process not complete. This bit indicates that a remote fault has been detected. Once set, it remains set until it is cleared by reading register 1 via the management interface or by PHY reset. RO, Remote fault condition detected Remote fault condition not detected. ...
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... Note: The OUI is 00-AA-00. Type Default OUI, bits [24:19]. RO 000000b Note: The OUI is 00-AA-00. The value is part of the PHY identifier and represents the RO 000101b device model number. The value is part of the PHY identifier and represents the RO 0x3 device revision number. ...
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... Programmer’s Visible State—82577 GbE PHY Table 15. Auto-Negotiation Link Partner Ability Register - Address 5 Bits Field 15 Next Page 14 Acknowledge 13 Remote Fault 12 Reserved 11 Asymmetric Pause 10 Pause Capable 100BASE-T4 9 Capability 100BASE-TX Full- 8 Duplex Capability 100BASE-TX Half- 7 Duplex Capability 10BASE-T Full- 6 Duplex Capability 10BASE-T Half- ...
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... Bits Field 15 Next Page 14 Acknowledge 13 Message Page 12 Acknowledge2 11 Toggle Message/ 10:0 Unformatted Code Field 55 82577 GbE PHY—Programmer’s Visible State Type Default 1b = Additional next pages to follow. R Sending last next page Reserved Formatted page. R Unformatted page Complies with message. R Cannot comply with message. ...
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... SC • Auto-negotiation completed. • Auto-negotiation enabled Master/slave configuration fault detected master/slave configuration fault detected. This bit is not valid when bit 15 is set Local PHY resolved to master Local PHY resolved to slave Local receiver is correct Local receiver is incorrect Remote receiver is correct Remote receiver is incorrect. ...
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... Reserved Idle Error 7:0 Count Table 21. Extended Status Register - Address 15 Bits Field 1000BASE-X Full- 15 Duplex 14:0 Reserved Table 22. PHY Control Register 2 - Address 18 Bits Field Resolve MDI/MDI Before Forced Speed Count False 14 Carrier Events Count Symbol 13 Errors 12:11 Reserved Automatic MDI/ ...
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... Reserved Type Default Reserved. This bit enables PHY diagnostics, which include IP phone detection and TDR cable diagnostics not recommended to enable this bit in normal operation (when the link is active). This bit does not need to be R/W set for link analysis cable diagnostics. ...
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... Table 23. Rx Error Counter Characteristics Count False Carrier Events Bit 9 of the PHY Control register manually sets the MDI/MDI-X configuration if automatic MDI-X is disabled (refer to Table 24. MDI/MDI-X Configuration Parameters Automatic MDI/MDI-X The mapping of the transmitter and receiver to pins for MDI and MDI-X configuration ...
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... Link Enable bit (Register 23, bit 13) should be set for each loopback mode. It also indicates whether the loopback mode sets the Link Status bit and when the PHY is ready to receive data. Table 27. Loopback Bit (Register 0, Bit 14) Settings for Loopback Mode ...
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... If automatic downshift is enabled and the PHY fails to auto-negotiate at 1000BASE-T, the PHY falls back to attempt connection at 100BASE-TX and, subsequently, 10BASE-T. This cycle repeats. If the link is broken at any speed, the PHY restarts this process by re- R/W GX attempting connection at the highest possible speed (1000BASE-T). ...
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... Reserved If LNK_EN is set, the PHY attempts to bring up a link with a remote partner and monitors the MDI for link pulses. If LNK_EN is cleared, the PHY takes down any active link, goes into standby, and does not respond to link pulses R/W X from a remote link partner. In standby, IP phone detect and TDR functions are available ...
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... Underflow 3 Receive Status Change 2 Link Status Change Automatic Speed 1 Downshift 0 MDINT_N Enable 1. MDINT_N is asserted (active low) if MII interrupt pending = 1b. 63 82577 GbE PHY—Programmer’s Visible State Type Default Reserved Interrupt enabled. R Interrupt disabled Interrupt enabled. R Interrupt disabled Interrupt enabled. R Interrupt disabled ...
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... Event completed. RO Event has not completed. If the management frame preamble is suppressed (MF preamble suppression, Register 0, bit 6 possible for the PHY to lose synchronization if there is a glitch at the interface. The PHY can recover if a single frame with a preamble is sent to the PHY. The RO MDIO sync lost interrupt can be used to detect loss of synchronization and, thus, enable recovery ...
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... Asymmetric PAUSE 65 82577 GbE PHY—Programmer’s Visible State Type Default This bit indicates that the PHY is in standby mode and is ready to perform IP phone detection or TDR cable diagnostics. The PHY enters standby mode when LNK_EN is cleared (Register 23, bit 13 = 0b) and exits ...
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... Programmer’s Visible State—82577 GbE PHY Table 35. LED Control Register 1 - Address 27 Bits Field Two-Color Mode 15 LED_100/LED_10 Two-Color Mode 14 LED_LNK/ACT/ LED_1000 LED_10 Extended 13 Modes LED_100 Extended 12 Modes LED_1000 Extended 11 Modes LED_LNK/ACT 10 Extended Modes 9:8 Reserved 7:4 LED Blink Pattern Pause R/W ...
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... Field 3:2 LED Pause Duration 1 LED Output Disable 0 Pulse Stretch 0 67 82577 GbE PHY—Programmer’s Visible State Type Default The pulse duration for the setting, Register 27, bits 3:2 = 11b, can be programmed in the range steps using the extended register set. R/W 00b 00b = Stretch LED events ...
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... Programmer’s Visible State—82577 GbE PHY Table 36. LED Control Register 2 - Address 28 Bits Field 15:12 LED_10 11:8 LED_100 7:4 LED_1000 LED_LNK/ 3:0 ACT Type Default R/W X See description for bits 3:0. R/W X See description for bits 3:0. R/W X See description for bits 3:0. ...
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... Address LED Blink Pattern 13:8 Frequency 7:0 LED Blink Pattern 69 82577 GbE PHY—Programmer’s Visible State Type Default Select LED blink pattern register set. 00b = Select register set for LED_LNK/ACT. R/W 00b 01b = Select register set for LED_1000. 10b = Select register set for LED_100. ...
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... Programmer’s Visible State—82577 GbE PHY Table 38. Diagnostics Control Register (Linking Disabled) - Address 30 Bits Field 15:14 TDR Request 13:12 TDR Tx Dim 11:10 TDR Rx Dim 9:0 Reserved Type Default Automatic TDR analysis is enabled by setting TDR request to11b. All ten combinations of pairs are analyzed in sequence, and the results are available in Register 31 ...
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... A value of 11b indicates that the results for this pair are invalid. An invalid result usually occurs when unexpected pulses are received during the TDR operation. For example, from a remote PHY that is also doing TDR or trying to brink up a link. When an invalid result is indicated, the distance in bits 9:2 of Register 31 is 0xFF and should be ignored ...
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... Programmer’s Visible State—82577 GbE PHY Table 39. Diagnostics Status Register (Linking Disabled) - Address 31 Bits Field Short Between Pairs 11 X and B Short Between Pairs 10 X and A 9:2 Distance to Fault 1:0 Pair Indication Type Default The first time these bits are read after automatic ...
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... Excessive Pair Skew 73 82577 GbE PHY—Programmer’s Visible State Type Default Reserved. If this bit is set, the PHY has detected that received pair 2 (RJ-45 pins 4 and 5) and pair 3 (RJ-45 pins 7 and 8) have crossed over Pairs C and D are swapped (1000BASE-T only Pairs C and D are not swapped (1000BASE-T only) ...
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... Wait IPG expires until the Back Pressure In- band bit is cleared Reserved Active Power Down Enable (sD3 Enable) When set to 1b, the Intel® 5 Series Express 0b 6 Chipsetneeds to enter MAC power down mode. Reserved. This bit is reset by power on reset 1b 5 only. ...
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... RO/V This register counts the number of times that a successfully transmitted packet encountered a single collision. This register only increments if transmits are enabled and the 82577 is in half-duplex mode. Table 48. Excessive Collisions Count - ECOL PHY Address 01, Page 778, Register Bit Type 31:0 RO/V 75 82577 GbE PHY— ...
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... The behavior of this counter is slightly different in the 82577 relative to the 82542. For the 82577, this counter does not increment for streaming transmits that are deferred due to TX IPG. Table 53. Transmit with No CRS - TNCRS PHY Address 01, Page 778, Register Bit Type 31:0 ...
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... PCIe Registers Table 54. PCIe FIFOs Control/Status PHY Address 01, Page 770, Register 16) Name Reserved Rx FIFO overflow Reserved Tx FIFO overflow Reserved Table 55. PCIe Power Management Control PHY Address 01, Page 770, Register 17 Name Burst enable Reserved Reserved Reserved Reserved Reserved Reserved Reserved 77 82577 GbE PHY—Programmer’s Visible State ...
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... Timeouts PHY Address 01, Page 770, Register 21 Name Reserved Reserved Reserved 1. All in-band timeouts are multiplied by 1000 while in SMBus mode. Table 59. PCIe Kstate Minimum Duration Timeout PHY Address 01, Page 770, Register 1 23 Name Reserved EI_min_dur timeout 1. All in-band timeouts are multiplied by 1000 while in SMBus mode. ...
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... General Registers Table 60. 82577 Capability PHY Address 01, Page 776, Register 19 Name Reserved Reserved 802.1Q & 802.1p Receive Side Scaling 2 Tx and 2 Rx Queues Energy Detect AC/DC Auto Link Speed Connect Reserved Reserved Ability to initiate a team The 82577 Capability register is loaded with the set of capabilities that correspond to the selected the 82577 SKU ...
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... SMBus Address Valid SMBus Address 1. This register is reset only on internal power on reset. Table 63. Shadow Receive Address Low0 – SRAL0 PHY Address 01, Page 0, Registers 27-28 Attribute Bit(s) RW 31:0 Table 64. Shadow Receive Address High0 – RAH0 PHY Address 01, Page 0, Registers 29 Attribute Bit(s) RW 15:0 RW 17:16 RO 30: ...
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... Table 65. LED Configuration PHY Address 01, Page 0, Register 30 Name Default Blink rate 0b LED2 Blink 0b LED2 Invert 0b LED2 Mode 110b LED1 Blink 0b LED1 Invert 0b LED1 Mode 111b LED0 Blink 1b LED0 Invert 0b LED0 Mode 100b NOTES: 1. When LED Blink mode is enabled the appropriate Led Invert bit should be set to zero. ...
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... If the given address is in the [0..15] range, meaning PHY registers, the functionality remains unchanged. There are two valid instructions: 1. Address Set – 0x11 – Wake up space address is set for either reading or writing. ...
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... PHYADD = The 82577’s address from the MDI register d. REGADD = 0x12 (data cycle for write) e. DATA = YYYY (data to be written to the register) 8.10.2 Host Wake Up Control Status Register Description Table 66. Receive Control – RCTL PHY Address 01, Page 800, Register 0 Attribute Bit( ...
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... Programmer’s Visible State—82577 GbE PHY Note: All wake up registers (page 800-801 except CTRL and IPAV) are not cleared with PHY reset is asserted only cleared when internal power on reset is de-asserted or when cleared by the software device driver. Note: Access to page 800/801 should be done only in 10 Mb/s and 100 Mb/s. ...
Page 92
... Table 68. Wake Up Filter Control – WUFC PHY Address 01, Page 800, Register 2 Attribute Bit( This register is used to enable each of the pre-defined and flexible filters for wake up support. A value of 1b means the filter is turned on, and a value of 0b means the filter is turned off. 85 82577 GbE PHY—Programmer’s Visible State ...
Page 93
... This register is used to record statistics about all wake up packets received. Note that packets that match multiple criteria might set multiple bits. Writing any bit clears that bit. This register is not cleared when PHY reset is asserted only cleared when internal power on reset is de-asserted or when cleared by the software device driver. Initial ...
Page 94
... Table 70. Receive Address Low – RAL PHY Address 01, Page 800, Registers 16- 4*n (n=0…6) Attribute Bit(s) RW 31:0 1. While “n” is the exact unicast/multicast address entry and it is equals to 0,1,…6. Table 71. Receive Address High – RAH PHY Address 01, Page 800, Registers 18-19 + ...
Page 95
... Table 73. Shared Receive Address High – SHRAH PHY Address 01, Page 800, Registers 46-47 + 4*n (n=0…2) Attribute Bit(s) RW 15:0 RO 17:16 RO 30: Table 74. Shared Receive Address High 3 – SHRAH[3] PHY Address 01, Page 800, Registers 58-59 Attribute Bit(s) RW 15:0 RO 17:16 RO 29: Initial Value Receive Address Low (RAL) The lower 32 bits of the 48-bit Ethernet address n (n=0… ...
Page 96
... The IPv4 address table is used to store the three IPv4 addresses for IPv4 request packets and directed IPv4 packet wake ups 3-entry table with the following format: Table 77. IPv6 Address Table – IP6AT PHY Address 01, Page 800, Registers 88-89 + 2*n (n=0…3) Attribute ...
Page 97
... The complete multicast offset options are: 00b 01b 10b 11b Figure 9. Multicast Table Array Algorithm Table 79. Flexible Filter Value Table LSB– FFVT_01 PHY Address 01, Page 800, Registers 256 + 2*n (n=0…127) Attribute Bit(s) RW 7:0 RW 15:8 There are 128 filter values. The flexible filter value is used to store the one value for each byte location in a packet for each flexible filter ...
Page 98
... Flexible Filter Enable bits of the WUFC register (WUFC.FLXn). Table 81. Flexible Filter Value Table – FFVT_45 PHY Address 01, Page 800, Registers 512 + 2*n (n=0…127) Attribute Bit(s) RW 7:0 RW 15:8 Table 82. Flexible Filter Mask Table – FFMT PHY Address 01, Page 800, Registers 768 + n (n=0…127) Attribute Bit( ...
Page 99
... Before writing to the flexible filter length table the software device driver must first disable the flexible filters by writing zeros to the Flexible Filter Enable bits of the WUFC register (WUFC.FLXn). Table 84. Flexible Filter Length Table – FFLT45 PHY Address 01, Page 800, Registers 904 + n (n=0…1) Attribute Bit(s) ...
Page 100
... Descriptor Region is used to define vendor specific information and the location, allocated space, and read and write permissions for each region. The Manageability (ME) Region contains the code and configuration data for ME functions such as Intel Active Management Technology. The system BIOS is contained in the BIOS Region. The ...
Page 101
... Intel representative. 2. The GbE region must be part of the original image flashed onto the part. 3. For Intel LAN tools and drivers to work correctly, the BIOS must set the VSCC register(s) correctly. There are two sets of VSCC registers, the upper (UVSCC) and lower (LVSCC) ...
Page 102
... Protected Range register of the GbE LAN Memory Mapped Configuration registers must be set to their default value of 0x0000 0000. (The GbE Protected Range registers are described in the Intel 5. The sector size of the NVM must equal 256 bytes KB. When a Flash device that uses sector erase is used, the GbE region size must equal 128 KB ...
Page 103
... Network Interface Card (NIC) or LAN on Motherboard (LOM), and thus unique for each copy of the NVM image. The first three bytes are vendor specific - for example, the IA is equal to [00 AA 00] or [00 A0 C9] for Intel products. The value from this field is loaded into the Receive Address Register 0 (RAL0/RAH0). ...
Page 104
... This field is reserved and must be set to 000b. 1b Reserved, must be set to 1b. 0000b These bits are reserved and must be set to 0000b. Auxiliary Power Indication If set and if PM Ena is set, D3cold wake-up is advertised in the Intel 5 Series Express Chipset of the PCI function AUX power AUX power. Power Management Enable (PME-WoL) Enables asserting PME in the PCI function at any power state ...
Page 105
... Reserved, set to 1b. 001b Reserved, set to 001b. Enable PHY Power Down When set, enables PHY power down at DMoff/ and no WoL. This bit is loaded to the PHY Power Down Enable bit in the 0b Extended Device Control (CTRL_EXT) register Enable PHY power down PHY always powered up. ...
Page 106
... Dynamic Clock 0 gating 99 82577 GbE PHY—Non-Volatile Memory (NVM) Default Description PHY Device Type Indicates that the PHY is connected to the MAC and resulted mode of operation of the MAC/PHY link buses. 00b = 82577. 00b 01b = Reserved. 10b = Reserved. 11b = Reserved. 01 Reserved, should be set to 1b. ...
Page 107
... This configuration area also includes the PHY tuning (tuning for IEEE) in the NVM. Since this bit 0b is set default, PHY tuning does not take effect until the LAN driver and/or firmware loads. When disabled, the extended LAN connected device configuration area is ignored. Loaded to the EXTCNF_CTRL register ...
Page 108
... OEM Configuration Defaults (Word 0x17) This word defines the OEM fields for the PHY power management parameters loaded to the PHY Control (PHY_CTRL) register. Bits Name 15 Reserved 14 GbE Disable 13:12 Reserved GbE Disable in 11 non-D0a LPLU Enable in 10 non-D0a LPLU Enable in ...
Page 109
... LED Configuration Defaults (Word 0x18) This NVM word specifies the hardware defaults for the LED Control (LEDCTL) register fields controlling the LED1 (LINK_1000), LED0 (LINK/ACTIVITY) and LED2 (LINK_100) output behaviors. Refer to the Intel Schematics for LED connection details. Also, outputs. Note: Due to the architecture of the 82577 the customized LEDs settings are written to the 82577 by the LAN driver ...
Page 110
... Reserved 1 Reserved 0 APM Enable 103 82577 GbE PHY—Non-Volatile Memory (NVM) Mnemonic State / Event Indicated Asserted when either 10 or 1000 Mb/s link is established and maintained. Asserted when either 100 or 1000 Mb/s link is established and maintained. Asserted when any speed link is established and maintained ...
Page 111
... Description 0x0 Reserved, set to 0x0. 0b Enable PLL stop in K1. 0b Enables K0s mode when PHY link speed is 10/100 Mb/s. 0b Enables K0s mode when PHY link speed is 1000 Mb/s. 0b Reserved, set to 0b. 0b When set to 1b enables K1 low power mode. Default Description 0x10EA Reserved ...
Page 112
... Reserved (Word 0x22) Bits Name 15:0 Reserved 9.3.1.26 Reserved (Word 0x23) Bits Name 15:0 Reserved 105 82577 GbE PHY—Non-Volatile Memory (NVM) Default Description 0xBAAD Reserved Default Description 0xBAAD Reserved ...
Page 113
... Non-Volatile Memory (NVM)—82577 GbE PHY 9.3.1.27 Reserved (Word 0x24) Bits Name 15 Reserved 14 Reserved 13:0 Reserved 9.3.1.28 Reserved (Word 0x25) Bits Name 15 Reserved 14:8 Reserved 7 Reserved 6:5 Reserved 4 Reserved 3:0 Reserved 9.3.1.29 Reserved (Word 0x26) Bits Name 15 Reserved 14 Reserved 13:12 Reserved ...
Page 114
... The boot agent software configuration is controlled by the NVM with the main setup options stored in word 0x30. These options are those that can be changed by using the Control-S setup menu or by using the IBA Intel Boot Agent utility. Note that these settings only apply to Boot Agent software. ...
Page 115
... Word 0x31 contains settings that can be programmed by an OEM or network administrator to customize the operation of the software. These settings cannot be changed from within the Control-S setup menu or the IBA Intel Boot Agent utility. The lower byte contains settings that would typically be configured by a network administrator using the Intel Boot Agent utility ...
Page 116
... DPS 1 DTM 0 DSM 109 82577 GbE PHY—Non-Volatile Memory (NVM) Description Disable Protocol Select If set to 1b, no changes to the boot protocol is allowed. The default for this bit is 0b; allow changes to the boot protocol. Disable Title Message If set to 1b, the title message displaying the version of the boot agent is suppressed ...
Page 117
... Non-Volatile Memory (NVM)—82577 GbE PHY 9.3.2.1.3 Boot Agent Configuration Customization Options (Word 0x32) Word 0x32 is used to store the version of the boot agent that is stored in the Flash image. When the Boot Agent loads, it can check this value to determine if any first-time configuration needs to be performed. The agent then updates this word with its version ...
Page 118
... Reserved 11 LOM 10:0 Reserved 111 82577 GbE PHY—Non-Volatile Memory (NVM) Description Signature These bits must be set to 01b to indicate that this word has been programmed by the agent or other configuration software. Reserved, must be set to 0x00. iSCSI boot capability not present (0b default). ...
Page 119
... The nine-digit Printed Board Assembly (PBA) number used for Intel manufactured Network Interface Cards (NICs) and Lan on Motherboard (LOMs) are stored in a four- byte field. The dash itself is not stored, neither is the first digit of the 3-digit suffix always zero for the affected products. Note that through the course of hardware ECOs, the suffix field (byte 4) is incremented ...
Page 120
... Intel 5 Series Express Chipset/82577 NVM Contents This section lists the NVM contents for the Intel 82577. Table 17. LAN NVM Contents Word 0x00:0x02 Ethernet Individual Address 0x03:0x04 Reserved 0x05 Image Version Information 0x06:0x07 Reserved 0x08:0x09 PBA Bytes 0x0A PCI Init Control Word ...
Page 121
... Non-Volatile Memory (NVM)—82577 GbE PHY Note: This page intentionally left blank. 114 ...
Page 122
... The following listed exceptions use network ordering (also called big endian). Using the previous example, a 16-bit field (such as EtherType) is stored in a CSR in the following manner: Dword aligned or Word aligned DW address ( 115 ® 82577 GbE PHY—Intel 5 Series Express Chipset MAC Programming Interface First First Byte 3 Byte 2 0x03 0x02 ... ...
Page 123
... Intel 5 Series Express Chipset MAC Programming Interface—82577 GbE PHY The following exceptions use network ordering: • All ETherType fields The normal notation as it appears in text books, etc use network ordering. For example, the following MAC address: 00-A0-C9-00-00-00. The order on the network is 00, then A0, then C9, etc ...
Page 124
... GbE PHY—Intel 5 Series Express Chipset MAC Programming Interface Table 18. These registers are ordered by Abbreviation Name General Register Descriptions CTRL Device Control Register STATUS Device Status Register STRAP ...
Page 125
... Intel 5 Series Express Chipset MAC Programming Interface—82577 GbE PHY Offset 0x000C0 0x000C4 0x000C8 0x000D0 0x000D8 0x000E0 0x00100 0x00104 0x02008 0x02170 0x02160 0x02168 0x02800 0x02804 0x02808 0x02810 0x02818 0x02820 0x02828 0x0282C 0x02C00 0x02C08 0x05000 0x05008 0x05200-0x0527C 0x05400 + 8*n (n=0…6) 0x05404 + 8*n (n=0… ...
Page 126
... Certain registers maintain an alias address designed for backward compatibility with software written for the previous devices. Registers that have an alias address can be accessed by software at either the new offset or the alias offset recommended that software that is written solely for the Intel 82577 use the new address offset. 119 ® ...
Page 127
... MAC on the asserting edge of the PHY link signal. When asserted, the CTRL.FD bit sets duplex. 0b Reserved. 0b Reserved. 0b Reserved. Reads as 0. 0b0 Reserved. Memory Error Handling Enable (MEHE). When set to 1b, the Intel® Series Express Chipset reaction to correctable and uncorrectable memory errors detection are activated. 1b Reserved. 0x0 Reserved. 0b Reserved. ...
Page 128
... This register's address is also reflected at address 0x00004 for legacy reasons. Neither the software driver nor firmware should use it since it might be unsupported in next generations. 121 ® 82577 GbE PHY—Intel 5 Series Express Chipset MAC Programming Interface Reset Transmit Flow Control Enable (TFCE). Indicates that the MAC transmits 0b flow control packets (XON and XOFF frames) based on receiver fullness ...
Page 129
... Intel 5 Series Express Chipset MAC Programming Interface—82577 GbE PHY 10.2.1.1.2 Device Status Register - STATUS (0x00008; RO) Bits Attribute 0 RO/V 1 RO/V 3:2 RO/V 4 RO/V 5 RO/V 7:6 RO/V 8 RO/V 9 RW/V/C 10 RW/V/C 18: RO/V 29: RO/SN Reset Description Full Duplex (FD Half duplex Full duplex. Reflects duplex setting of the MAC and/or link. ...
Page 130
... MAC only, if the MAC speed setting has been forced via software (CTRL.SPEED). Speed indications are mapped as shown below: • 00b = 10 Mb/s • 01b = 100 Mb/s • 10b = 1000 Mb/s • 11b = 1000 Mb/s 123 ® 82577 GbE PHY—Intel 5 Series Express Chipset MAC Programming Interface ...
Page 131
... Series Express Chipset MAC Programming Interface—82577 GbE PHY 10.2.1.1.3 Strapping Option Register - STRAP (0x0000C; RO) This register reflects the values of the soft strapping options fetched from the NVM descriptor in the Intel the MAC following LAN_RST# or global reset (PCI reset assertion). Bit(s) Type ...
Page 132
... GbE PHY—Intel 5 Series Express Chipset MAC Programming Interface Reset Driver loaded (DRV_LOAD). This bit should be set by the driver after it was loaded and cleared when the driver unloads or after a soft reset. The ...
Page 133
... Intel 5 Series Express Chipset MAC Programming Interface—82577 GbE PHY 10.2.1.1.5 MDI Control Register - MDIC (0x00020; RW) Bits Type 15:0 RW/V 20:16 RW/V 25:21 RW/V 27:26 RW/V 28 RW/V 29 RW This register is used by software to read or write Management Data Interface (MDI) registers in the 82577. ...
Page 134
... Enable dynamic clock stop. When this bit is set to 1b, 0b clk is always ticking. The default value is 0b (hardware and NVM). Invalid Image CSUM. When cleared, this bit indicates to the Intel NVM 0b programming tools that the image CSUM needs to be corrected. When set the CSUM is assumed to be correct ...
Page 135
... Intel 5 Series Express Chipset MAC Programming Interface—82577 GbE PHY Bits Type 9:7 RW/SN 10 RW/SN 11 RW/SN 12 RW/SN 13 RW/SN 14 RW/SN 15 RW/SN 19:16 RW/SN 20 RW/SN 26:21 RW/SN 27 RW/SN 31:28 RW/SN Reset Description 0x0 Reserved. Enable MDIO Watchdog Timer (MDIOWatchEna). When set to 0b, the 100 ms MDIO watchdog timer is enabled ...
Page 136
... RO 10.2.1.1.9 Flow Control Transmit Timer Value - FCTTV (0x00170; RW) Bit Type 15:0 RW 31:16 RO 129 ® 82577 GbE PHY—Intel 5 Series Express Chipset MAC Programming Interface Reset 0b Reserved. 0b Reserved. 00b Reserved. 0x0 Reserved. Hardware/Software CRC Mismatch Trigger. When set to 1b the MAC ...
Page 137
... Intel 5 Series Express Chipset MAC Programming Interface—82577 GbE PHY The 16-bit value in the TTV field is inserted into a transmitted frame (either XOFF frames or any PAUSE frame value in any software transmitted packets). It counts in units of slot time. If software needs to send an XON frame, it must set TTV to zero prior to initiating the PAUSE frame ...
Page 138
... RW/SN 1 RW/SN 0 RW/SN 131 ® 82577 GbE PHY—Intel 5 Series Express Chipset MAC Programming Interface Reset 0x0 Reserved. Extended LCD Length. Size (in Dwords) of the extended PHY configuration area loaded from Extended Configuration word 2 in the NVM 0x0 extended configuration area is disabled by the LCD Write Enable field in word 0x14 in the NVM, this length must be set to zero ...
Page 139
... Intel 5 Series Express Chipset MAC Programming Interface—82577 GbE PHY 10.2.1.1.14 PCIE Analog Configuration - PCIEANACFG (0x00F18; RW) Bit Type 0 RW 6:1 RW 31:7 RO 10.2.1.1.15 Packet Buffer Allocation - PBA (0x01000; RW) Bit Type 4:0 RW 15:5 RO 20:16 RO 31:21 RO This register sets the on-chip receive and transmit storage allocation ratio. ...
Page 140
... RO 23:16 RW 31:24 RW 133 ® 82577 GbE PHY—Intel 5 Series Express Chipset MAC Programming Interface Reset Correctable Error Count (Corr_err_cnt). This counter is incremented every 0x0 time a correctable error is detected. The counter stops counting after reaching 0xFF. Cleared by read. Uncorrectable Error Count (uncorr_err_cnt). This counter is incremented 0x0 every time an uncorrectable error is detected ...
Page 141
... Receiver Timer Interrupt (RXT0). Set when the timer expires. LCAPD Exit Interrupt (LCAPD). Set when the Intel 0b Chipset takes the MAC out of LCAPD state. 0b MDIO Access Complete (MDAC). Set when the MDIO access completes. ...
Page 142
... For example, if the interval is programmed to 500d, the network controller guarantees the CPU is not interrupted by the network controller for 128 ms from the last interrupt. 135 ® 82577 GbE PHY—Intel 5 Series Express Chipset MAC Programming Interface Reset Small Receive Packet Detected (SRPD). Indicates that a packet size < ...
Page 143
... Intel 5 Series Express Chipset MAC Programming Interface—82577 GbE PHY Inversely, inter-interrupt interval value can be calculated as: inter-interrupt interval = (256 x 10 The optimal performance setting for this register is very system and configuration specific. An initial suggested range for the interval value is 65--5580 (28B - 15CC). ...
Page 144
... RXO. Sets mask for receiver overrun. Set on receive data FIFO overrun. 0b RXT0. Sets mask for receiver timer interrupt. LCAPD. Sets mask for LCAPD interrupt. LCAPD mask is set after reset to 0b enable LCAPD interrupt (driven by Intel 0b MDAC. Sets mask for MDIO access complete interrupt. 00b Reserved. ...
Page 145
... Intel 5 Series Express Chipset MAC Programming Interface—82577 GbE PHY 10.2.1.2.5 Interrupt Mask Clear Register - IMC (0x000D8; WO) Bit Type 11: 31:23 RO Software uses this register to disable an interrupt. Interrupts are presented to the bus interface only when the mask bit and the cause bit is a 1b. The status of the ...
Page 146
... RW 13: 139 ® 82577 GbE PHY—Intel 5 Series Express Chipset MAC Programming Interface Reset IAM_VALUE. When the CTRL_EXT.IAME bit is set and the 0x0 ICR.INT_ASSERTED=1, an ICR read or write has the side effect of writing the contents of this register to the IMC register. Reset Reserved ...
Page 147
... Intel 5 Series Express Chipset MAC Programming Interface—82577 GbE PHY Bit Type 15 RW 17:16 RW 21: 30: Reset Description Broadcast Accept Mode (BAM Ignore broadcast (unless it matches through exact or imperfect 0b filters Accept broadcast packets. Receive Buffer Size (BSIZE). RCTL.BSEX – zero: 00b = 2048 bytes. ...
Page 148
... The SECRC bit controls whether hardware strips the Ethernet CRC from the received packet. This stripping occurs prior to any checksum calculations. The stripped CRC is not DMA'd to host memory and is not included in the length reported in the descriptor. 141 ® 82577 GbE PHY—Intel 5 Series Express Chipset MAC Programming Interface Free Buffer Threshold 1/2 1/4 ...
Page 149
... Intel 5 Series Express Chipset MAC Programming Interface—82577 GbE PHY 10.2.1.3.2 Receive Control Register 1 - RCTL1 (0x00104; RW) Bit Type 7:0 RO 9:8 RW 11:10 RW 15:12 RO 17:16 RW 24: 30: Reset Reserved. This bit represents a hardware reset of the receive-related portion of the device in previous controllers, but is no longer applicable. ...
Page 150
... When early receive is used in parallel to the packet split feature, the minimum value of the ERT register should be bigger than the header size to enable the actual packet split. 143 ® 82577 GbE PHY—Intel 5 Series Express Chipset MAC Programming Interface Reset Receive Threshold Value (RxThreshold). This threshold is in units of eight 0x0 bytes ...
Page 151
... Intel 5 Series Express Chipset MAC Programming Interface—82577 GbE PHY 10.2.1.3.4 Packet Split Receive Control Register - PSRCTL (0x02170) Bit Type 6 13:8 RW 15:14 RO 21:16 RW 23:22 RO 29:24 RW 31:30 RO Note: If software sets a buffer size to zero, all buffers following that one must be set to zero as well ...
Page 152
... RW X This register contains the upper 32 bits of the 64-bit descriptor base address. 145 ® 82577 GbE PHY—Intel 5 Series Express Chipset MAC Programming Interface Reset 0x0 Reserved. Must be written with 0. Receive Threshold High (RTH). FIFO high water mark for flow control 0x0 transmission ...
Page 153
... Intel 5 Series Express Chipset MAC Programming Interface—82577 GbE PHY 10.2.1.3.9 Receive Descriptor Length Queue- RDLEN (0x02808; RW) Bits Type Reset 6:0 RO 0x0 19:7 RW 0x0 31:20 RO 0x0 This register sets the number of bytes allocated for descriptors in the circular descriptor buffer. It must be 128-byte aligned. ...
Page 154
... PCI configuration space CLS field) must not represent greater than 31 descriptors. Note: When (WTHRESH = 0b) or (WTHRESH = 1b and GRAN = 1b) only descriptors with the RS bit set is written back. 147 ® 82577 GbE PHY—Intel 5 Series Express Chipset MAC Programming Interface Description Prefetch Threshold (PTHRESH). Reserved. Host Threshold (HTHRESH). Reserved. ...
Page 155
... Intel 5 Series Express Chipset MAC Programming Interface—82577 GbE PHY PTHRESH is used to control when a prefetch of descriptors is considered. This threshold refers to the number of valid, unprocessed receive descriptors the chip has in its on- chip buffer. If this number drops below PTHRESH, the algorithm considers pre-fetching descriptors from host memory ...
Page 156
... RSS hash. Only one of the two options is reported in the Rx descriptor. The RXCSUM.PCSD affect is shown in the following table: 149 ® 82577 GbE PHY—Intel 5 Series Express Chipset MAC Programming Interface Description SIZE. If the interrupt is enabled any receive packet of size <= SIZE asserts an interrupt. SIZE is specified in bytes and includes the headers and the CRC. It does not include the VLAN header in size calculation stripped ...
Page 157
... Intel 5 Series Express Chipset MAC Programming Interface—82577 GbE PHY RXCSUM.PCSD Legacy Rx descriptor (RCTL.DTYP = 00b) Extended or header split Rx descriptor (RCTL.DTYP = 01b) PCSS IPPCSE: The PCSS and the IPPCSE control the packet checksum calculation. As previously noted, the packet checksum shares the same location as the RSS field. The packet checksum is reported in the receive descriptor when the RXCSUM ...
Page 158
... Multicast offset in the CTRL equals 00b. The complete multicast offset options are: 151 ® 82577 GbE PHY—Intel 5 Series Express Chipset MAC Programming Interface Description iSCSI Disable (ISCSI_DIS). Disable the iSCSI filtering for header split functionality ...
Page 159
... Intel 5 Series Express Chipset MAC Programming Interface—82577 GbE PHY Multicast Offset 00b 01b 10b 11b MO1:0] Figure 19. Multicast Table Array Algorithm 10.2.1.3.20 Receive Address Low - RAL (0x05400 + 8*n (n=0…6); RW) While “n” is the exact unicast/multicast address entry and it is equals to 0,1,…6. ...
Page 160
... RW 0b 153 ® 82577 GbE PHY—Intel 5 Series Express Chipset MAC Programming Interface Description Receive Address High (RAH). The upper 16 bits of the 48-bit Ethernet address n (n=0, 1…6). RAH 0 is loaded from word 2 in the NVM. Address Select (ASEL). Selects how the address used. Decoded as follows: 00b = Destination address (must be set to this in normal mode) ...
Page 161
... Intel 5 Series Express Chipset MAC Programming Interface—82577 GbE PHY 10.2.1.3.24 Shared Receive Address High 3 - SHRAH[3] (0x05454; RW) Bits Type Reset 15 17:16 RO 00b 29:19 RO 0x0 10.2.1.3.25 Multiple Receive Queues Command register - MRQC (0x05818; RW) Bits Type Reset 1:0 RW 0x00b 15:2 0x0 21:16 ...
Page 162
... RW 0x0 31:24 RW 0x0 155 ® 82577 GbE PHY—Intel 5 Series Express Chipset MAC Programming Interface 31:24 23:16 Tag 4*n+2 Tag 4*n+1 Description CPU INDX 0. CPU index for Tag 4*n (n=0,1,…31). Reserved. QUE INDX 0. Queue Index for Tag 4*n (n=0,1,…31). ...
Page 163
... Intel 5 Series Express Chipset MAC Programming Interface—82577 GbE PHY 10.2.1.4 Transmit Register Descriptions 10.2.1.4.1 Transmit Control Register - TCTL (0x00400; RW) Bits Type Reset 11:4 RW 0x0F 21:12 RW 0x3F 22 RW 27:25 RW 0x0 28 1b 30:29 RW 01b Two fields deserve special mention: CT and COLD. Software might choose to abort packet transmission in less than the Ethernet mandated 16 collisions ...
Page 164
... In summary, the recommended TIPG value to achieve 802.3 compliant minimum transmit IPG values in full and half duplex is 0x00702008. 157 ® 82577 GbE PHY—Intel 5 Series Express Chipset MAC Programming Interface Description IPG Transmit Time (IPGT). Specifies the IPG length for back-to-back transmissions equal to [(IPGT+ bit time ...
Page 165
... Intel 5 Series Express Chipset MAC Programming Interface—82577 GbE PHY 10.2.1.4.3 Adaptive IFS Throttle - AIT (0x00458; RW) Bits Type Reset 15:0 RW 0x0000 31:16 RO 0x0000 Adaptive IFS throttles back-to-back transmissions in the transmit packet buffer and delays their transfer to the CSMA/CD transmit function, and thus can be used to delay the transmission of back-to-back packets on the wire ...
Page 166
... ONLY applies to transmit descriptor operations where (a) interrupt-based reporting is requested (RS set) and (b) the use of the timer function is requested (IDE is set). 159 ® 82577 GbE PHY—Intel 5 Series Express Chipset MAC Programming Interface Description Reserved. Ignore on write. Reads back as 0b. Descriptor Length (LEN). ...
Page 167
... Intel 5 Series Express Chipset MAC Programming Interface—82577 GbE PHY This feature operates by initiating a countdown timer upon successfully transmitting the buffer subsequent transmit delayed-interrupt is scheduled BEFORE the timer expires, the timer is re-initialized to the programmed value and re-starts its countdown. When the timer expires, a transmit-complete interrupt (ICR.TXDW) is generated ...
Page 168
... GRAN = 1 (descriptor granularity): PTHRESH = 0..31 WTHRESH = 0..31 HTHRESH = 0..31 GRAN = 0 (cacheline granularity): PTHRESH = 0..3 (for 16 descriptors cacheline - 256 bytes) 161 ® 82577 GbE PHY—Intel 5 Series Express Chipset MAC Programming Interface Description Prefetch Threshold (PTHRESH). Reserved. Host Threshold (HTHRESH). Reserved. Write-Back Threshold (WTHRESH). ...
Page 169
... Intel 5 Series Express Chipset MAC Programming Interface—82577 GbE PHY WTHRESH = 0..3 HTHRESH = 0..4 Note: For any WTHRESH value other than zero - The packet and absolute timers must get a non zero value for the WTHRESH feature to take affect. Note: Since the default value for write-back threshold is zero, descriptors are normally written back as soon as they are processed ...
Page 170
... If there is NO VAUX, then the PME Status bits should be cleared by: — LAN_RST# or PCI reset — PCI reset de-assertion — Explicit software clear 163 ® 82577 GbE PHY—Intel 5 Series Express Chipset MAC Programming Interface Description Advance Power Management Enable (APME APM Wakeup is enabled APM Wakeup is disabled. ...
Page 171
... Intel 5 Series Express Chipset MAC Programming Interface—82577 GbE PHY 10.2.1.5.2 Wake Up Filter Control Register - WUFC (0x05808; RW) Bits Type Reset 14:8 RO 0x0 31:2 RO 0x0 This register is used to enable each of the pre-defined and flexible filters for wake up support. A value of 1b means the filter is turned on, and a value of 0b means the filter is turned off ...
Page 172
... The IP6AT has the following format: Bits Type Reset 31 165 ® 82577 GbE PHY—Intel 5 Series Express Chipset MAC Programming Interface Description FLX4. Flexible Filter 4 Match. FLX5. Flexible Filter 5 Match. Reserved. Description Reserved. V41. IPv4 Address 1 Valid. ...
Page 173
... Intel 5 Series Express Chipset MAC Programming Interface—82577 GbE PHY 10.2.1.5.7 Flexible Filter Length Table - FFLT (0x05F00 + 8*n (n=0…5); RW) There are six flexible filters Lengths. The flexible filter length table stores the minimum packet lengths required to pass each of the flexible filters. Any packets that are shorter than the programmed length does not pass that filter ...
Page 174
... Flexible Filter Enable bits of the Wake Up Filter Control register (WUFC.FLXn). 167 ® 82577 GbE PHY—Intel 5 Series Express Chipset MAC Programming Interface Description Value 1. Value of filter 1 byte n (n=0, 1… 127). Value 2. Value of filter 2 byte n (n=0, 1… 127). ...
Page 175
... Intel 5 Series Express Chipset MAC Programming Interface—82577 GbE PHY Note: This page intentionally left blank. 168 ...
Page 176
... Recommended operation conditions require accuracy of power supply of +/-5% relative to the nominal voltage. 3. Maximum ratings are referenced to ground (VSS). 169 82577 GbE PHY—Electrical and Timing Specifications Parameter Case Temperature Under Bias Storage Temperature Range 3.3 Vdc I/O Voltage Analog 1.0 Vdc I/O Voltage 3 ...
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... Electrical and Timing Specifications—82577 GbE PHY 11.2.2 Recommended Operating Conditions Symbol Ta 1. For normal device operation, adhere to the limits in this table. Sustained operations of a device at conditions exceeding these values, even if they are within the absolute maximum rating limits, can result in permanent device damage or impaired device reliability. Device functionality to stated Vdc and V ac limits is not guaranteed if conditions exceed recommended operating conditions ...
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... Cc Collector capacitance @ VCB=-5 Vdc MHz Transition frequency @ mA, VCE = -5 Vdc 100 fT Recommended transistor Ib 171 82577 GbE PHY—Electrical and Timing Specifications Description Time from 10% to 90% mark Voltage dip allowed in ramp and 90% Min: 0.8*V(min)/Rise time (max) Max: 0.8*V(max)/Rise time (min) Voltage range for normal operating ...
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... External Components Description Name PNP Transistor Q1 1.0 Vdc Regulator 1. This component has been used in previous designs; however, Intel does not specifically recommend or endorse any component. 11.3.2 Power Detection Threshold Table 86. Power Detection Threshold Symbol V1a High-threshold for 3.3 Vdc supply V2a Low-threshold for 3 ...
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... VOL VCC = Min IOL = -9 mA VOH VCC = Min Ipullup Ileakage 173 82577 GbE PHY—Electrical and Timing Specifications Bus Description Size 1 Open-drain I/O 1 Open-drain I(H)/O with Snap back NMOS ESD cell 1 Open-drain I(H)/O with Snap back NMOS ESD cell Minimum Typical -0 ...
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... Electrical and Timing Specifications—82577 GbE PHY Signal Name RSVD1_VCC3P3 RSVD2_VCC3P3 LED[2:0] TDI TMS TDO TCK 11.4.3 Input Buffer Only Parameter Conditions VIL VIH Ipullup Ileakage Ci Signal Name Internal Power On Reset/ LAN_DISABLE_N TEST_EN PE_RST_N Bus Description Size I/O, PU ...
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... Maximum time to transition to a valid T tx-idle-set-to-idle electrical idle after sending an EIOS Maximum time to transition to valid T differential signaling after leaving tx-idle-to-diff-data electrical idle 175 82577 GbE PHY—Electrical and Timing Specifications 1.25 GT/s Units Min Max Each UI is 800 pS +/- 799.92 800.08 ps 100 ppm ...
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... Electrical and Timing Specifications—82577 GbE PHY Note: Figure 20 is for informational purposes only. Do not use for actual eye comparisons. Figure 20. Transmitter Eye Diagram 600 mV 400 -400 mV -600 mV 0 100 175 625 Time (pS) Note: Not To Scale 700 800 176 ...
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... Rx differential Vdc impedance rx-diff-dc Z rx-high-imp-dc- DC input CM impedance for V>0 pos Z rx-high-imp-dc- DC input CM impedance for V<0 neg V Electrical idle detect threshold rx-idle-det-diffp-p 177 82577 GbE PHY—Electrical and Timing Specifications 1.25 GT/s Units Min Max 799.92 800.08 ps 0.175 1.2 Vdc 0.175 1.2 Vdc ...
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... Note: The 82577 has integrated PCIe termination that results in attenuating the voltage swing of the PCIe clock supplied by the Intel® 5 Series Express Chipset. This is in compliance with the PCIe CEM 1.1 specification. More detail is available in the Intel® 5 Series Family PDG. ...
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... MHz through 300 MHz 300.1 MHz through 500 MHz 11.6 Mechanical Body Size (mm) 6x6 mm 179 82577 GbE PHY—Electrical and Timing Specifications Condition 1500 Vrms (min) 2250 Vdc (min) 400 H (min) 350 H (min (max) 0.6 dB (max) 0.8 dB (max) 1 ...
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... Df/f @25°C ±30 [ppm] o Df/f ±30 [ppm [pF] load Df/f ±5 ppm per year o Parallel ). Refer to the crystal design guidelines in the Intel L Symbol/Parameter Conditions f @25 [°C] o Vp -20 to +70 opr f/f o XTAL_IN High Time XTAL_IN Low Time XTAL_IN Rise 10% to 90% XTAL_IN Fall ...
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... If required, contact your Intel representative for information about implementing the conditioning circuit. For placement and layout guidelines, refer to the Intel® 5 Series Family Platform Design Guide (PDG). ...
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... Schematic and Board Layout Checklists The 82577 schematic and board layout checklists can be found at www.intel.com. 183 82577 GbE PHY—Schematic and Board Layout Checklists ...
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... Schematic and Board Layout Checklists—82577 GbE PHY Note: This page intentionally left blank. 184 ...
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... Reference Schematics The 82577 reference schematics can be found at www.intel.com. 185 82577 GbE PHY—Reference Schematics ...
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... Reference Schematics—82577 GbE PHY Note: This page intentionally left blank. 186 ...
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... Models Contact your local Intel representative for access. 187 82577 GbE PHY—Models ...
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... Models—82577 GbE PHY Note: This page intentionally left blank. 188 ...