SLXT973QE Cortina Systems Inc, SLXT973QE Datasheet - Page 65

• Manufacturer Part Number: SLXT973QE
• Manufacturer: Cortina Systems Inc

Specifications of SLXT973QE

• Lead Free Status / RoHS Status: Not Compliant

LXT973 Transceiver
Datasheet
249426, Revision 6.0
13 July 2007
12.0
Table 14
Table 15
Cortina Systems
Register Definitions
The LXT973 Transceiver register set includes 16 registers per port. Refer to
complete register listing.
Base Registers 0 through 8 are defined in accordance with the “Reconciliation Sublayer
and Media Independent Interface” and “Physical Layer Link Signaling for 10/100 Mbps
Auto-Negotiation” sections of the IEEE 802.3 specification.
Additional registers are defined in accordance with the IEEE 802.3 specification for adding
unique chip functions.
Common Register Set
Register Bit Descriptions
®
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
Address
Bit Type
R/W
LHR
WO
RO
16
27
AC
0
1
2
3
4
5
6
7
8
Control Register
Status Register
PHY Identification Register 1
PHY Identification Register 2
Auto-Negotiation Advertisement Register
Auto-Negotiation Link Partner Base Page Ability Register Refer to
Auto-Negotiation Expansion Register
Auto-Negotiation Next Page Transmit Register
Auto-Negotiation Link Partner Received Next Page
Register
Port Configuration Register
Special Function Register
Read and Write capable
Read Only
Write Only
Auto Clear on Read
Latched from external pins on reset
Register Name
Description
Refer to
Refer to
Refer to
Refer to
Refer to
Refer to
Refer to
Refer to
Refer to
Refer to
12.0 Register Definitions
Table 24 on page 72
Table 25 on page 73
Table 26 on page 74
Table 16 on page 66
Table 17 on page 67
Table 18 on page 68
Table 19 on page 68
Table 20 on page 69
Table 21 on page 70
Table 22 on page 71
Table 23 on page 72
Bit Definitions
Table 14
Page 65
for a