SLXT973QE Cortina Systems Inc, SLXT973QE Datasheet - Page 66

• Manufacturer Part Number: SLXT973QE
• Manufacturer: Cortina Systems Inc

Specifications of SLXT973QE

• Lead Free Status / RoHS Status: Not Compliant

LXT973 Transceiver
Datasheet
249426, Revision 6.0
13 July 2007
Table 16
Cortina Systems
Control Register (Address 0)
®
1. Refer to
2. During a hardware reset, all LHR information is latched in from the pins. During a software reset (Register
3. LHR = Latched on Hardware Reset. Register bits 0.12, 0.13 and 0.8 are initialized based on the pin
4. The Isolate function (Register bit 0.10) three-states all port MAC interface outputs. On the input side,
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
0.5:0
0.15
0.14
0.13
0.12
0.11
0.10
Bit
0.9
0.8
0.7
0.6
bit 0.15), the LHR information is not re-read from the pins. This information reverts back to the information
that was read in during the hardware reset. During a hardware reset, register information is unavailable for
1 ms after de-assertion of the reset. During a software reset (Register bit 0.15) the registers are available
for reading. The reset bit should be polled to see when the part has completed reset.
configuration value.
TXEN and TXER are ignored.
RESET
Loopback
Speed Selection
(LSB)
Auto-Negotiation
Enable
Power-Down
Isolate
Restart
Auto-Negotiation
Duplex Mode
Collision Test
Speed Selection
(MSB)
Reserved
Table 15 on page 65
Name
for Register Bit Descriptions.
1 = PHY reset
0 = Normal operation
1 = Enable loopback mode
0 = Disable loopback mode
0.6
1 = Enable Auto-Negotiation Process
0 = Disable Auto-Negotiation Process
1 = Power-Down
0 = Normal operation
1 = Electrically isolate PHY from MII
0 = normal operation
1 = Restart Auto-Negotiation Process
0 = Normal operation
1 = Full-duplex
0 = Half-duplex
1 = Enable COL signal test
0 = Disable COL signal test
0.6
Write as 0, ignore on Read
1
1
0
0
1
1
0
0
0.13
0.13
1 = Reserved
0 = 1000 Mbps (not allowed)
1 = 100 Mbps
0 = 10 Mbps
1 = Reserved
0 = 1000 Mbps (not allowed)
1 = 100 Mbps
0 = 10 Mbps
Description
12.0 Register Definitions
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
AC
AC
1,2
Default
000000
Note 2
Note 3
Note 3
Note 4
Note 3
LHR
LHR
LHR
Page 66
00
0
0
0
0
0
0