DJLXT971ALE.A4 Cortina Systems Inc, DJLXT971ALE.A4 Datasheet
DJLXT971ALE.A4
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DJLXT971ALE.A4 Summary of contents
Page 1
... FX fiber networks. The LXT971A PHY supports full-duplex operation at 10 Mbps and 100 Mbps. Operating conditions for the LXT971A PHY can be set using auto-negotiation, parallel detection, or manual control. The LXT971A PHY is fabricated with an advanced CMOS process and requires only a single 2.5/3.3 V power supply. (This Datasheet also supports the LXT971 PHY.) ...
Page 2
... Cortina Systems logo are the trademarks or registered trademarks of Cortina Systems, Inc. and its subsidiaries in the U.S. and other countries. Other names and brands may be claimed as the property of others. Copyright © 2007 Cortina Systems, Inc. All rights reserved. ® Cortina Systems LXT971A Single-Port 10/100 Mbps PHY Transceiver Legal Disclaimers ® PRODUCTS. Page 2 ...
Page 3
... Mbps Operation ............................................................................................................. 49 5.8.1 10BASE-T Preamble Handling .............................................................................. 49 5.8.2 10BASE-T Carrier Sense....................................................................................... 49 5.8.3 10BASE-T Dribble Bits .......................................................................................... 49 5.8.4 10BASE-T Link Integrity Test ................................................................................ 50 5.8.5 Link Failure ............................................................................................................ 50 5.8.6 10BASE-T SQE (Heartbeat) .................................................................................. 50 5.8.7 10BASE-T Jabber .................................................................................................. 50 ® Cortina Systems LXT971A Single-Port 10/100 Mbps PHY Transceiver Contents Page 3 ...
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... Typical Twisted-Pair Interface ............................................................................................ 54 6.3 Fiber Interface..................................................................................................................... 57 7.0 Electrical Specifications ............................................................................................................. 61 7.1 DC Electrical Parameters ................................................................................................... 61 7.2 AC Timing Diagrams and Parameters ................................................................................ 65 8.0 Register Definitions - IEEE Base Registers .............................................................................. 78 9.0 Register Definitions - Product-Specific Registers ................................................................... 86 10.0 Package Specifications............................................................................................................... 94 ® Cortina Systems LXT971A Single-Port 10/100 Mbps PHY Transceiver Contents Page 4 ...
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... Typical Twisted-Pair Interface - Switch ......................................................................................... 55 23 Typical Twisted-Pair Interface - NIC ..............................................................................................56 24 Typical Media Independent Interface ............................................................................................ 57 25 Typical Interface - LXT971A PHY to 3.3 V Fiber PHY................................................................... 58 26 Typical Interface LXT971A PHY Fiber PHY........................................................................ 59 27 Typical Interface - LXT971A PHY to Triple PECL-to-PECL Logic Translator............................... 60 28 100BASE-TX Receive Timing - 4B Mode ...................................................................................... 66 29 100BASE-TX Transmit Timing - 4B Mode ...
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... Power-Up Timing ........................................................................................................................... 76 44 RESET_L Pulse Width and Recovery Timing ............................................................................... 77 Register Set for IEEE Base Registers ........................................................................................... Control Register - Address 0, Hex 0 ..............................................................................................79 47 MII Status Register #1 - Address 1, Hex 1 .................................................................................... 80 48 PHY Identification Register 1 - Address 2, Hex 2 .......................................................................... 81 ® Cortina Systems LXT971A Single-Port 10/100 Mbps PHY Transceiver Tables Page 6 ...
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... LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 49 PHY Identification Register 2 - Address 3, Hex 3 .......................................................................... 81 50 Auto-Negotiation Advertisement Register - Address 4, Hex 4....................................................... 82 51 Auto-Negotiation Link Partner Base Page Ability Register - Address 5, Hex 5 ............................. 83 52 Auto-Negotiation Expansion - Address 6, Hex 6 ........................................................................... 84 53 Auto-Negotiation Next Page Transmit Register - Address 7, Hex 7 .............................................. 84 54 Auto-Negotiation Link Partner Next Page Receive Register - Address 8, Hex 8 ...
Page 8
... Section 6.3, “The Fiber Modified text and added a new bullet in first and second set of bullets under Replaced Figure 27 “Recommended LXT971A-to-3.3 V Fiber PHY Interface Replaced Figure 28 “Recommended LXT971A-to-5 V Fiber PHY Interface Added Section 10.1, Top Label Markings. Modified Section 14.0, Product Ordering Information: ...
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... Table 14 “Device ID Register”. Added a new Section 4.3, “The Fiber Interface”. Replaced Figure 25 “Recommended LXT971A-to-3.3 V Fiber PHY Interface Added Figure 26 “Recommended LXT971A-to-5 V Fiber PHY Interface Added Figure 27 “ON Semiconductor Triple PECL-to-LVPECL Logic Modified Table 17 “Absolute Maximum Ratings”. Modified Table 18 “Operating Conditions” ...
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... Register Definitions - IEEE Base Registers, on page 78 9.0, Register Definitions - Product-Specific Registers, on page 86 1.2 Related Documents Table 1 Related Documents Fiber Optic PHYs Connecting a PECL Interface Application Note ® Cortina Systems 100BASE-FX Fiber Optic PHYs - Connecting a PECL/ LVPECL Interface Application Note ® ...
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... Set Collision COL Detect RX_CLK Serial -to- RXD[3:0] Parallel RXDV Converter Carrier Sense CRS Data Valid Error Detect RX_ER ® Cortina Systems LXT971A Single-Port 10/100 Mbps PHY Transceiver Clock Generator + Manchester * 10 TP OSP Encoder Driver Pulse - Scrambler 100 Shaper & Encoder + ECL ...
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... Table 2 list the signal type abbreviations used in the signal tables. Table 2 PHY Signal Types Abbreviation AI Analog Input AO Analog Output I Input I/O Input/Output O Output OD Open Drain ® Cortina Systems LXT971A Single-Port 10/100 Mbps PHY Transceiver 3.0 Ball and Pin Assignments Definition Page 12 ...
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... RESET SLEW0 SLEW1 E ADDR0 ADDR1 F ADDR3 ADDR2 SD/ G ADDR4 TP_L H RBIAS TPFOP 1 ® Cortina Systems LXT971A Single-Port 10/100 Mbps PHY Transceiver TXD3 TXD0 RX_ER VCCD RX_ TXD2 TX_EN TX_ER CLK TX_ GND TXD1 GND CLK MDDIS GND VCCIO RXD3 LED/ GND ...
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... ADDR2 ADDR3 ADDR4 Table 3 LQFP Numeric Pin List (Sheet Pin Symbol 1 REFCLK/ MDDIS 4 RESET_L 5 TxSLEW0 6 TxSLEW1 7 GND 8 VCCIO GND 12 ADDR0 13 ADDR1 14 ADDR2 15 ADDR3 ® Cortina Systems LXT971A Single-Port 10/100 Mbps PHY Transceiver Type – – NC – NC – – 3.0 Ball and Pin Assignments ...
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... LED/CFG3 37 LED/CFG2 38 LED/CFG1 39 PWRDWN 40 VCCIO 41 GND 42 MDIO 43 MDC 44 45 RXD3 46 RXD2 47 RXD1 48 RXD0 49 RX_DV 50 GND 51 VCCD 52 RX_CLK 53 RX_ER ® Cortina Systems LXT971A Single-Port 10/100 Mbps PHY Transceiver Type I AI – – – – – – I/O I/O I/O I – – I – – ...
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... Revision 5.2 13 September 2007 Table 3 LQFP Numeric Pin List (Sheet Pin Symbol 54 TX_ER 55 TX_CLK 56 TX_EN 57 TXD0 58 TXD1 59 TXD2 60 TXD3 61 GND 62 COL 63 CRS 64 MDINT_L ® Cortina Systems LXT971A Single-Port 10/100 Mbps PHY Transceiver 3.0 Ball and Pin Assignments Type – Page 16 ...
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... Table 9, Configuration and LED Driver Signal Descriptions • Table 10, Power, Ground, No-Connect Signal Descriptions, on page 22 • Table 11, JTAG Test Signal Descriptions, on page 22 • Table 12, Pin Types and Modes, on page 23 ® Cortina Systems LXT971A Single-Port 10/100 Mbps PHY Transceiver Definition 4.0 Signal Descriptions Page 17 ...
Page 18
... RXD is a group of parallel signals that transition synchronously with O respect to RX_CLK. RXD[0] is the least-significant bit. Receive Data Valid. O The PHY asserts this signal when it drives valid data on RXD. This output is synchronous to RX_CLK. Receive Error. O Signals a receive error condition has occurred. This output is synchronous to RX_CLK. ...
Page 19
... I Clock for the MDIO serial data channel. Maximum frequency is 8 MHz. Management Data Input/Output. I/O Bidirectional serial data channel for PHY/STA communication. Management Data Interrupt. When register bit 18 active Low output on this pin OD indicates status change. Interrupt is cleared by reading Register 19. ...
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... Fiber mode - Connect SD/TP_L High (register bit 16.0 = 1). Twisted-Pair Mode. For normal operation that uses the twisted-pair mode, connect SD/ TP_L to ground. Fiber Mode. For normal operation that uses the fiber mode, SD/TP_L acts as the SD input from the fiber PHY. Type Signal Description I I Address. ...
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... PAUSE I When set High, the PHY advertises Pause capabilities during auto-negotiation. Sleep. When set High, this pin enables the PHY to go into a low- SLEEP I power sleep mode. The value of this pin can be overridden by register bit 16.6 when in managed mode. Power Down. ...
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... These pins do not need to be terminated If a JTAG port is not used ® Cortina Systems LXT971A Single-Port 10/100 Mbps PHY Transceiver Symbol Type Digital Power. VCCD – Requires a 3.3 V power supply. GND – Ground. MII Power. Requires either a 3 2.5 V supply. Must be supplied VCCIO – ...
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... SFTPWRDN DL HWPWRDN HZ HZ with HZ with ISOLATE ID SLEEP DL • Driven High (Logic 1) • Driven Low (Logic 0) • High Impedance • Internal Pull-Down (Weak) ® Cortina Systems LXT971A Single-Port 10/100 Mbps PHY Transceiver Tx/Rx RX_ER COL CLKS Output Output Output Output Active DL DL ...
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... Section 5.10, Boundary Scan (JTAG 1149.1) Functions, on page 52 5.1 Device Overview The LXT971A PHY is a single-port Fast Ethernet 10/100 PHY that supports 10 Mbps and 100 Mbps networks. It complies with applicable requirements of IEEE 802.3. It directly drives either a 100BASE-TX line or a 10BASE-T line. ...
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... The network interface port consists of five external pins (two differential signal pairs and a signal detect pin). The I/O pins are shared between twisted-pair (TP) and fiber. For specific pin assignments, see The LXT971A PHY output drivers can generate one of the following outputs: • 100BASE-TX • 10BASE-T • ...
Page 26
... Remote Fault indications received from its link partner. The LXT971A PHY ORs both fault conditions to set bit 1.4 to ‘1’. register bit 1.4 is set once and clears to ‘0’ when it is read. In fiber operations, the far-end fault detection process requires idles to establish link ...
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... Datasheet 249414, Revision 5.2 13 September 2007 • When register bit 16 the LXT971A PHY does not transmit far end fault code. It continues to transmit idle code and may or may not drop link depending on the setting for register bit 16.14. • When register bit 16 transmission of the far end fault code is enabled. The LXT971A PHY transmits far end fault code if fault conditions are detected by the SD/ TP_L pin ...
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... The MDIO addressing protocol allows a controller to communicate with multiple PHYs. Pins ADDR[4:0] can be used to determine the PHY device address that is selected. 5.2.3.1.2 MDIO Frame Structure The physical interface consists of a data line (MDIO) and clock line (MDC). The frame structure is shown in MDIO Interface timing is given in Figure 4 ...
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... Register 18 provides interrupt enable and mask functions. Setting register bit 18 enables the device to request interrupt via the MDINT_L pin. An active Low on this pin indicates a status change on the LXT971A PHY. Interrupts may be caused by any of the following four conditions: — Auto-negotiation complete — ...
Page 30
... Section 5.4.3, Reset • Section 5.4.4, Hardware Configuration Settings When the LXT971A PHY is first powered on, reset, or encounters a link failure state, it checks the MDIO register configuration bits to determine the line speed and operating conditions to use for the network link. Table 13 shows the LXT971A PHY initialization sequence. The configuration bits may be set by the Hardware Control or MDIO interface. ® ...
Page 31
... MDIO Control Mode and Hardware Control Mode In the MDIO Control mode, the LXT971A PHY reads the Hardware Control Interface pins to set the initial (default) values of the MDIO registers. Once the initial values are set, bit control reverts to the MDIO interface. ...
Page 32
... During this mode, the LXT971A PHY still responds to management transactions (MDC/ MDIO). In this mode the power consumption is minimized, and the supply current is reduced below the maximum value. If the LXT971A PHY detects activity on the twisted- pair inputs, it comes out of the sleep state and checks for link link is detected in from seconds (the time is programmable) it reverts to the low power sleep state ...
Page 33
... During a software reset, registers are available for reading. To see when the LXT971A PHY has completed reset, the reset bit can be polled (that is, register bit 0.15 = 0). For pin settings used during a hardware reset, see Settings ...
Page 34
... Establishing Link Figure 9 shows an overview of link establishment for the LXT971A PHY. Note: When a link is established by using parallel detection, the LXT971A PHY sets the duplex mode to half-duplex, as defined by the IEEE 802.3 standard. ® Cortina Systems LXT971A Single-Port 10/100 Mbps PHY Transceiver 3 ...
Page 35
... Base Page Exchange By exchanging Base Pages, the LXT971A PHY and its link partner communicate their capabilities to each other. Both sides must receive at least three consecutive identical base pages for negotiation to continue. Each side identifies the highest common capabilities that both sides support, and each side configures itself accordingly. ...
Page 36
... Manual Next Page Exchange “Next Page Exchange” information is additional information that exceeds the information required by Base Page exchange and that is sent by “Next Pages”. The LXT971A PHY fully supports the IEEE 802.3 standard method of negotiation through the Next Page exchange. ...
Page 37
... The LXT971A PHY implements the Media Independent Interface (MII) as defined by the IEEE 802.3 standard. Separate channels are provided for transmitting data from the MAC to the LXT971A PHY (TXD), and for passing data received from the line (RXD) to the MAC. Each channel has its own clock, data bus, and control signals. ...
Page 38
... Clocking for 100BASE-X TX_CLK RX_CLK XI ® Cortina Systems LXT971A Single-Port 10/100 Mbps PHY Transceiver 2.5 MHz during auto-negotiation and 10BASE-T Data & Idle 2.5 MHz during auto-negotiation and 10BASE-T Data & Idle Constant 25 MHz 2.5 MHz during auto-negotiation 2.5 MHz during auto-negotiation Constant 25 MHz 5 ...
Page 39
... Carrier Sense Carrier Sense (CRS asynchronous output. • CRS is always generated when the LXT971A PHY receives a packet from the line. • CRS is also generated when the LXT971A PHY is in half-duplex mode when a packet is transmitted. Table 14 summarizes the conditions for assertion of carrier sense, data loopback, and collision signals ...
Page 40
... Error Signals When the LXT971A PHY is in 100 Mbps mode and receives an invalid symbol from the network, it asserts RX_ER and drives “0101” on the RXD pins. When the MAC asserts TX_ER, the LXT971A PHY drives “H” symbols out on the TPFOP/ N pins ...
Page 41
... Register 16 5.6.7.2 Internal Digital Loopback (Test Loopback) A test loopback function is provided for diagnostic testing of the LXT971A PHY. During test loopback, twisted-pair and fiber interfaces are disabled. Data transmitted by the MAC is internally looped back by the LXT971A PHY and returned to the MAC. Test loopback is available for both 100BASE-TX and 10BASE-T operation, and is enabled by setting the following register bits: • ...
Page 42
... During 100BASE-X operation, the LXT971A PHY transmits and receives 5-bit symbols across the network link. Figure 14 shows the structure of a standard frame packet in 100BASE-X mode. When the MAC is not actively transmitting data, the LXT971A PHY sends out Idle symbols on the line. As Figure 14 shows, the MAC starts each transmission with a preamble pattern ...
Page 43
... S3 to Parallel S4 Note: In 100BASE-FX mode, the LXT971A PHY transmits and receives NRZI signals across the LVPECL interface. An external 100BASE-FX PHY module is required to complete the fiber connection. To enable 100BASE-FX operation, auto-negotiation must be disabled and fiber mode selected. Figure 16 shows normal reception with no errors. ...
Page 44
... TXD<3:0> P CRS COL Upon detection of a collision, the COL output is asserted and remains asserted for the duration of the collision as shown in Figure 19 100BASE-TX Transmission with Collision TX_CLK TX_EN TXD<3:0> P CRS COL ® Cortina Systems LXT971A Single-Port 10/100 Mbps PHY Transceiver Figure 19. ...
Page 45
... Sublayer PMD Sublayer 5.7.3.1 Physical Coding Sublayer The Physical Coding Sublayer (PCS) provides the MII interface, as well as the 4B/5B encoding/decoding function. For 100BASE-TX and 100BASE-FX operation, the PCS layer provides IDLE symbols to the PMD-layer line driver as long as TX_EN is de-asserted. ® Cortina Systems ...
Page 46
... The /J/ and /K/ (SSD) code groups are always sent in pairs, and /K/ follows /J/. 3. The /T/ and /R/ (ESD) code groups are always sent in pairs, and /R/ follows /T /H/ (Error) code group is used to signal an error condition. ® Cortina Systems LXT971A Single-Port 10/100 Mbps PHY Transceiver 5B Code Name Interpretation ...
Page 47
... Link Failure Override The LXT971A PHY normally transmits data packets only if it detects the link is up. Setting register bit 16. overrides this function, allowing the LXT971A PHY to transmit data packets even when the link is down. This feature is provided as a transmit diagnostic tool. ...
Page 48
... CRS de-assertion is not aligned with TX_EN de-assertion on transmit loopbacks in half-duplex mode. 5.7.3.2.4 Receive Data Valid The LXT971A PHY asserts RX_DV to indicate that the received data maps to valid symbols. In 100 Mbps operation, RX_DV is active with the first nibble of preamble. 5.7.3.3 Twisted-Pair Physical Medium Dependent Sublayer ...
Page 49
... CRS is asserted coincident with the start of the preamble. RX_DV is held Low for the duration of the preamble. When RX_DV is asserted, the very first two nibbles driven by the LXT971A PHY are the SFD “5D” hex followed by the body of the packet. ...
Page 50
... By default, the Signal Quality Error (SQE) or heartbeat function is disabled on the LXT971A PHY. To enable this function, set register bit 16 When this function is enabled, the LXT971A PHY asserts its COL output for bit times (BT) after each packet. For SQE timing parameters, see on page 73 ...
Page 51
... Monitoring Next Page Exchange The LXT971A PHY offers an Alternate Next Page mode to simplify the next page exchange process. Normally, register bit 6.1 (Page Received) remains set until read. When Alternate Next Page mode is enabled, register bit 6.1 is automatically cleared whenever a new negotiation process takes place ...
Page 52
... Note: The direct drive LED outputs in this diagram are shown as active Low. 5.10 Boundary Scan (JTAG 1149.1) Functions The LXT971A PHY includes a IEEE 1149.1 boundary scan test port for board level testing. All digital input, output, and input/output pins are accessible. Note: For the related BSDL file, contact your local sales office or access the Cortina website (www ...
Page 53
... Update 4 System Function 5.10.5 Device ID Register Table 18 lists the bits for the Device ID register. For the current version of the JEDEC continuation characters, see the specification update for the LXT971A PHY. Table 18 Device ID Register Bits 31:28 Bits 27:12 Version Part ID (Hex) XXXX 03CB 1 ...
Page 54
... Application Information 6.1 Magnetics Information The LXT971A PHY requires a 1:1 ratio for both the receive and transmit transformers. The transformer isolation voltage should be rated protect the circuitry from static voltages across the connectors and cables. For transformer/magnetics requirements, see Table 19 ...
Page 55
... V current source. A separate ferrite bead (rated at 50 mA) should be used to supply center tap current. 2. The 100 Ω transmit load termination resistor typically required is integrated in the PHY. 3. Magnetics without a receive pair center-tap do not require termination. 4. RJ-45 connections shown are for a standard switch application. For a standard NIC RJ-45 setup, ...
Page 56
... V current source. A separate ferrite bead (rated at 50 mA) should be used to supply center-tap current. 2. The 100 Ω transmit load termination resistor typically required is integrated in the PHY. 3. Magnetics without a receive pair center tap do not require termination. 4. RJ-45 connections shown for standard NIC. TX/RX crossover may be required for repeater and switch applications. ® ...
Page 57
... PHY crosstalk amplification in power-down, loopback, and reset states. (See the fiber interface application note.) • The receive pair should be DC-coupled with an emitter current path for the fiber PHY. • The signal detect pin should be DC-coupled with an emitter current path for the fiber PHY ...
Page 58
... The receive pair should be AC-coupled with an emitter current path for the fiber PHY and re-biased to 3.3 V LVPECL input levels. • The signal detect pin fiber PHY interface should use the logic translator circuitry as shown in Figure 26 shows a typical example of an interface between the LXT971A PHY and fiber PHY ...
Page 59
... LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 Figure 26 Typical Interface LXT971A PHY Fiber PHY TPFON TPFOP LXT97x PHY SD/TP_L TPFIN TPFIP 1. Refer to the manufacturers’ recommendations for termination circuitry. 2. See Figure 26 ® Cortina Systems LXT971A Single-Port 10/100 Mbps PHY Transceiver + ...
Page 60
... LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 Figure 27 (a close-up view of PHY and a PECL-to-PECL logic translator. Figure 27 Typical Interface - LXT971A PHY to Triple PECL-to-PECL Logic Translator 0.01 μ Ω PECL Input Signal (5V Fiber Txcvr) 130 Ω ® Cortina Systems LXT971A Single-Port 10/100 Mbps PHY Transceiver ...
Page 61
... Revision 5.2 13 September 2007 7.0 Electrical Specifications This chapter includes test specifications for the LXT971A PHY. These specifications are guaranteed by test except where noted “by design”. Caution: Exceeding the absolute maximum rating values may cause permanent damage. Functional operation under these conditions is not implied. ...
Page 62
... MII digital I/O pins are tolerant inputs. 2. Typical values are at 25 °C and are for design aid only, not guaranteed, and not subject to production testing. 3. Parameter is guaranteed by design and not subject to production testing. ® Cortina Systems LXT971A Single-Port 10/100 Mbps PHY Transceiver Sym 2 - I/O Vccio I ...
Page 63
... Reset and Power-Up States – FX/TP Mode Configuration Fiber Mode (register bit 16 Twisted-Pair Mode (register bit 16 100BASE-FX Mode Normal Operation – SD Input from Fiber PHY Input Low Voltage Input High Voltage 1. Typical values are for design aid only, not guaranteed, and not subject to production testing. ...
Page 64
... LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 Table 28 100BASE-TX PHY Characteristics (Sheet Parameter Duty cycle distortion Overshoot/Undershoot Jitter (measured differentially) 1. Typical values are at 25 °C and are for design aid only, not guaranteed, and not subject to production testing. 2. Measured at the line side of the transformer, line replaced by 100 Ω (+/-1%) resistor. ...
Page 65
... Figure 38, Fast Link Pulse Timing, on page 74 • Figure 39, MDIO Input Timing, on page 75 • Figure 40, MDIO Output Timing, on page 75 • Figure 41, Power-Up Timing, on page 76 • Figure 42, RESET_L Pulse Width and Recovery Timing, on page 76 ® Cortina Systems LXT971A Single-Port 10/100 Mbps PHY Transceiver Symbol Min Typ Max T 50 – ...
Page 66
... Typical values are at 25 °C and are for design aid only, not guaranteed, and not subject to production testing (Bit Time) is the duration of one bit as transferred to and from the Mac and is the reciprocal of the bit rate. 100BASE-T bit time = 10 3. RX_ER is not shown in the figure. ® Cortina Systems LXT971A Single-Port 10/100 Mbps PHY Transceiver 250 Sym ...
Page 67
... Typical values are at 25 °C and are for design aid only, not guaranteed, and not subject to production testing (Bit Time) is the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit rate. 100BASE-T bit time = 10 3. TX_ER is not shown in the figure. ® Cortina Systems LXT971A Single-Port 10/100 Mbps PHY Transceiver 250ns 0ns ...
Page 68
... BT (Bit Time) is the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit rate. 100BASE-T bit time = 10 3. The RX_ER signal is not shown in the figure. ® Cortina Systems LXT971A Single-Port 10/100 Mbps PHY Transceiver 0ns 250ns t4 t3 ...
Page 69
... BT (Bit Time) is the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit rate. 100BASE-T bit time = 10 3. The TX_ER signal is not shown in the figure. ® Cortina Systems LXT971A Single-Port 10/100 Mbps PHY Transceiver 0ns 250ns t1 t2 ...
Page 70
... LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 Figure 32 10BASE-T Receive Timing RX_CLK RXD, RX_DV, RX_ER CRS TPFI COL Figure 33 10BASE-T Receive Timing RX_CLK RXD, RX_DV, RX_ER CRS TPI COL ® Cortina Systems LXT971A Single-Port 10/100 Mbps PHY Transceiver 7.2 AC Timing Diagrams and ...
Page 71
... Typical values are at 25 °C and are for design aid only, not guaranteed, and not subject to production testing (Bit Time) is the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit rate. 10BASE-T bit time = 10 ® Cortina Systems LXT971A Single-Port 10/100 Mbps PHY Transceiver 1 Sym Min Typ Max ...
Page 72
... Typical values are at 25 °C and are for design aid only, not guaranteed, and not subject to production testing (Bit Time) is the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit rate. 10BASE-T bit time = 10 ® Cortina Systems LXT971A Single-Port 10/100 Mbps PHY Transceiver ...
Page 73
... Parameter COL (SQE) Delay after TX_EN off COL (SQE) Pulse duration 1. Typical values are at 25 °C and are for design aid only, not guaranteed, and not subject to production testing. ® Cortina Systems LXT971A Single-Port 10/100 Mbps PHY Transceiver Symbol Min Typ ...
Page 74
... FLP burst width FLP burst to FLP burst Clock/Data pulses per burst 1. Typical values are at 25 °C and are for design aid only, not guaranteed, and not subject to production testing. ® Cortina Systems LXT971A Single-Port 10/100 Mbps PHY Transceiver Clock Pulse Data Pulse ...
Page 75
... STA MDC to MDIO output delay, sourced by PHY MDC period 1. Typical values are at 25° C and are for design aid only, not guaranteed, and not subject to production testing. ® Cortina Systems LXT971A Single-Port 10/100 Mbps PHY Transceiver 7.2 AC Timing Diagrams and Symbol ...
Page 76
... Power-up delay is specified as a maximum value because it refers to the PHY guaranteed performance. The PHY comes out of reset after a delay of no more than 300 μ s. System designers should consider this value as a minimum value. After threshold v1 is reached, the MAC should delay no less than 300 μ s before accessing the MDIO port ...
Page 77
... Reset Recovery Delay is specified as a maximum value because it refers to the PHY guaranteed performance. The PHY comes out of reset after a delay of no more than 300 μ s. System designers should consider this value as a minimum value. After de-asserting RESET_L, the MAC should delay no less than 300 μ ...
Page 78
... September 2007 8.0 Register Definitions - IEEE Base Registers This chapter includes definitions for the IEEE base registers used by the LXT971A PHY. Section 9.0, Register Definitions - Product-Specific Registers additional product-specific LXT971A PHY registers, which are defined in accordance with the IEEE 802.3 standard for adding unique device functions. ...
Page 79
... Mbps (not supported Reserved 0 = Disable auto-negotiation process 1 = Enable auto-negotiation process 0 = Normal operation 1 = Power-down 0 = Normal operation 1 = Electrically isolate PHY from MII 0 = Normal operation 1 = Restart auto-negotiation process 0 = Half-duplex 1 = Full-duplex 0 = Disable COL signal test 1 = Enable COL signal test 0.6 0.13 Speed Selected 0 ...
Page 80
... PHY able to perform half-duplex 100BASE PHY not able to operate at 10 Mbps full-duplex mode 1 = PHY able to operate at 10 Mbps in full-duplex mode 0 = PHY not able to operate at 10 Mbps in half- duplex 1 = PHY able to operate at 10 Mbps in half-duplex mode 0 = PHY not able to perform full-duplex 100BASE-T2 ...
Page 81
... Note: The Intel OUI is 00207B hex ® Cortina Systems LXT971A Single-Port 10/100 Mbps PHY Transceiver Description The PHY identifier is composed of bits 3 through 18 of the Organizationally Unique Identifier (OUI). Description The PHY identifier is composed of bits 19 through 24 of the OUI. 6 bits containing manufacturer’s part number. ...
Page 82
... Pause operation disabled Pause operation enabled for full-duplex link 100BASE-T4 capability is not available 100BASE-T4 capability is available. Note: The LXT971A PHY does not support 100BASE-T4 but allows this bit to be set to advertise in the auto-negotiation sequence for 100BASE-T4 operation. An external 100BASE-T4 PHY can be switched in if this capability is desired ...
Page 83
... Selector Field 5.4:0 S<4:0> Read Only ® Cortina Systems LXT971A Single-Port 10/100 Mbps PHY Transceiver 8.0 Register Definitions - IEEE Description 0 = Link Partner has no ability to send multiple pages Link Partner has ability to send multiple pages Link Partner has not received Link Code Word from the LXT971A PHY ...
Page 84
... Unformatted Code Field Read Only. R/W = Read/Write ® Cortina Systems LXT971A Single-Port 10/100 Mbps PHY Transceiver 8.0 Register Definitions - IEEE Description Ignore when read. This bit indicates the status of the auto-negotiation variable base page. It flags synchronization with the auto-negotiation state diagram, allowing detection of interrupted links ...
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... Unformatted Code Field Read Only. ® Cortina Systems LXT971A Single-Port 10/100 Mbps PHY Transceiver 8.0 Register Definitions - IEEE Description 0 = Link Partner has no additional next pages to send 1 = Link Partner has additional next pages to send 0 = Link Partner has not received Link Code Word from LXT971A PHY ...
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... Register Definitions - Product-Specific Registers This chapter includes definitions of product-specific LXT971A PHY registers that are defined in accordance with the IEEE 802.3 standard for adding unique device functions. (For definitions of the IEEE base registers used by the LXT971A PHY, see Register Definitions - IEEE Base • ...
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... Always LXT971A PHY is not operating 100BASE-TX mode LXT971A PHY is operating in 100BASE-TX mode LXT971A PHY is not transmitting a packet LXT971A PHY is transmitting a packet LXT971A PHY is not receiving a packet LXT971A PHY is receiving a packet collision Collision is occurring Link is down Link is up. 9.0 Register Definitions - Product-Specific Registers ...
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... Always Polarity is not reversed Polarity is reversed. Note: Polarity is not a valid status in 100 Mbps mode The LXT971A PHY is not Pause capable The LXT971A PHY is Pause capable error occurred 1 = Error occurred (Remote Fault, jabber, parallel detect fault) Note: The register bit is cleared when the registers that generate the error condition are read ...
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... SPEEDCHG 19.5 DUPLEXCHG 1. R/W = Read/Write Read Only Self Clearing. ® Cortina Systems LXT971A Single-Port 10/100 Mbps PHY Transceiver Description Write as ‘0’. Ignore on Read. Write as ‘0’. Ignore on Read. Mask for Auto Negotiate Complete not allow event to cause interrupt Enable event to cause interrupt. ...
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... Reserved 19.0 Reserved 1. R/W = Read/Write Read Only Self Clearing. ® Cortina Systems LXT971A Single-Port 10/100 Mbps PHY Transceiver Description Link Status Change Status Link Change has not occurred since last reading this register Link Change has occurred since last reading this register. ...
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... Collision status is the secondary LED driver. The LED changes state (blinks) when a collision occurs. 5. Values are approximations. Not guaranteed or production tested. ® Cortina Systems LXT971A Single-Port 10/100 Mbps PHY Transceiver Description 0000 =Display Speed Status (Continuous, Default) 0001 =Display Transmit Status (Stretched) ...
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... Show Symbol Error 26.8:6 Reserved 1. R/W = Read /Write Read Only ® Cortina Systems LXT971A Single-Port 10/100 Mbps PHY Transceiver Description 0000 =Display Speed Status 0001 =Display Transmit Status 0010 =Display Receive Status (Default) 0011 = Display Collision Status 0100 =Display Link Status ...
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... Values are approximations and may vary outside indicated values based upon implementation loading conditions. 2. R/W = Read/Write 3. Latch State during Reset is based on the state of hardware configuration pins at RESET_L. ® Cortina Systems LXT971A Single-Port 10/100 Mbps PHY Transceiver Description Write as ‘0’. Ignore on Read. Write as ‘0’. Ignore on Read. Write as ‘0’. Ignore on Read. Description Write as ‘ ...
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... REF. OPTION: PIN A1 IDENTIFIER 1.00 ± 0.10 INK OR LASER MARKING 1.26 ± 0.10 0.70 ± 0.025 0.26 ± 0.04 0.28 ± 0.10 SIDE VIEW ® Cortina Systems LXT971A Single-Port 10/100 Mbps PHY Transceiver B 0.70 REF TOP VIEW H 8 ...
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... Max A – 1.60 A 0.05 0. 1.35 1. 0.17 0.27 D 11.85 12.15 D 9.9 10 11.85 12.15 E 9.9 10 0.50 BSC L 0.45 0.75 L 1.00 REF 1 θ θ Basic Spacing between Centers ® Cortina Systems LXT971A Single-Port 10/100 Mbps PHY Transceiver 10.0 Package Specifications θ θ θ 3 Page 95 ...
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For additional product and ordering information: www.cortina-systems.com ~ End of Document ~ TM ...