CY7B923-JC Cypress Semiconductor Corp, CY7B923-JC Datasheet

CY7B923-JC

Manufacturer Part Number
CY7B923-JC
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7B923-JC

Lead Free Status / RoHS Status
Not Compliant

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Features
CY7B923 Transmitter Block Diagram
Cypress Semiconductor Corporation
Document #: 38-02017 Rev. *H
Fibre Channel-compliant
IBM ESCON
DVB-ASI-compliant
ATM-compliant
8B/10B-coded or 10-bit unencoded
Standard HOTLink
High-speed HOTLink: 160 to 400 Mbps for high-speed
applications
Transistor-transistor logic (TTL)-synchronous I/O
No external phase locked-loop (PLL) components
Triple positive emitter coupled logic (PECL) 100 K serial
outputs
Dual PECL 100 K serial inputs
Low-power: 350 mW (Tx), 650 mW (Rx)
Compatible with fiber-optic modules, coaxial cable, and twisted
pair media
Built-in self-test (BIST)
Single +5-V supply
28-pin small outline integrated circuit (SOIC)/plastic leaded
chip carrier (PLCC)/leadless chip carrier (LCC)
Pb-free packages available
0.8- bipolar complementary metal oxide semiconductor
(BiCMOS)
-compliant
: 160 to 330 Mbps
198 Champion Court
HOTLink
Functional Description
The CY7B923 HOTLink
receiver are point-to-point communications building blocks that
transfer data over high-speed serial links (fiber, coax, and twisted
pair). Standard HOTLink data rates range from 160 to 330 Mbps.
Higher speed HOTLink is also available for high-speed applica-
tions (160 to 400 Mbits/second).
connections to host systems or controllers.
Eight bits of user data or protocol information are loaded into the
HOTLink transmitter and are encoded. Serial data is shifted out
of the three differential PECL serial ports at the bit rate (which is
ten times the byte rate).
The HOTLink receiver accepts the serial bit stream at its differ-
ential line receiver inputs and, using a completely integrated PLL
clock synchronizer, recovers the timing information necessary
for data reconstruction. The bit stream is deserialized, decoded,
and checked for transmission errors. Recovered bytes are
presented in parallel to the receiving host along with a byte-rate
clock.
The 8B/10B encoder/decoder can be disabled in systems that
already encode or scramble the transmitted data. I/O signals are
available to create a seamless interface with both asynchronous
FIFOs (that is, CY7C42X) and clocked FIFOs (that is,
CY7C44X). A BIST pattern generator and checker allows testing
of the transmitter, receiver, and the connecting link as a part of a
system diagnostic check.
HOTLink devices are ideal for a variety of applications where a
parallel interface can be replaced with a high-speed
point-to-point serial link. Applications include interconnecting
workstations, servers, mass storage, and video transmission
equipment.
San Jose

Transmitter/Receiver
,
CA 95134-1709
transmitter and CY7B933 HOTLink
CY7B923, CY7B933
Figure 1
Revised October 14, 2010
illustrates typical
408-943-2600
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Related parts for CY7B923-JC

CY7B923-JC Summary of contents

Page 1

... Pb-free packages available ■ 0.8- bipolar complementary metal oxide semiconductor ■ (BiCMOS) CY7B923 Transmitter Block Diagram Cypress Semiconductor Corporation Document #: 38-02017 Rev. *H HOTLink Functional Description The CY7B923 HOTLink receiver are point-to-point communications building blocks that transfer data over high-speed serial links (fiber, coax, and twisted pair) ...

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... CY7B933 Receiver Block Diagram HOST Document #: 38-02017 Rev. *H Figure 1. HOTLink System Connections SERIAL LINK CY7B923, CY7B933 HOST Page [+] Feedback ...

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... Transmission Characters........................................... 20 Valid Data Characters (SC/D = LOW) ............................ 21 Valid Special Character Codes and Sequences (SC/D = HIGH) ............................................................................... 29 Maximum Ratings........................................................... 30 Operating Range............................................................. 30 CY7B923/CY7B933 Electrical Characteristics Over the Oper- ating Range ...................................................................... 30 Capacitance .................................................................... 31 Transmitter Switching Characteristics Over the Operating Range ............................................................................... 32 Receiver Switching Characteristics Over the Operating Range ...

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... Pin Configurations Figure 2. CY7B923 Transmitter Pin Configurations Document #: 38-02017 Rev. *H SOIC Top View OUTB OUTB OUTC OUTA OUTC+ OUTA FOTO CCN 25 BISTEN ENN 5 24 GND 6 ENA 23 MODE CCQ 7B923 RP CKW GND CCQ 9 20 SVS(D ) SC/D PLCC/LCC Top View ...

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... SI(INB ) INA A MODE BISTEN 4 REFCLK CCQ GND CKR RDY 7 22 7B933 V GND 21 8 CCQ V GND 9 20 CCN SC/D (Q RVS ( PLCC/LCC Top View 2726 RF REFCLK 25 5 GND CCQ RDY 7B933 GND CKR CCN CCQ RVS (Q ) GND SC 1213 1718 CY7B923, CY7B933 ) ) Page [+] Feedback ...

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... Pin Descriptions Table 1. CY7B923 HOTLink Transmitter Name I/O Description D TTL In Parallel data input. Data is clocked into the Transmitter on the rising edge of CKW if ENA is LOW (or on 0 the next rising CKW with ENN LOW). If ENA and ENN are HIGH, a Null character (K28.5) is sent. When b  ...

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... INB can be used as differential line receiver interchangeably with INA then INB can be used as differential line receiver interchangeably with INA. CC directly. When left floating (internal resistors hold the MODE pin at V aj or GND. CC CY7B923, CY7B933 , respectively. . 07 output. RVS has the same timing j and CC ...

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... V Power for internal circuitry. CCQ GND Ground. CY7B923 HOTLink Transmitter Block Diagram Description Input Register The input register holds the data to be processed by the HOTLink transmitter and allows the input timing to be made consistent with standard FIFOs. The input register is clocked by CKW and loaded with information on the D , SC/D, and SVS pins ...

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... Test logic includes the initialization and control for the BIST generator, the multiplexer for test mode clock distribution, and control logic to properly select the data encoding. Test logic is discussed in detail in CY7B923 HOTLink Transmitter Operating Mode Description on page 11. CY7B933 HOTLink Receiver Block Diagram ...

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... Data patterns (40 Mbytes per second for –400 devices) over several types of serial interface media. of data through the HOTLink CY7B923 transmitter pipeline. Data is latched into the transmitter on the rising edge of CKW when enabled by ENA or ENN asserted LOW with a 60% LOW/40% HIGH duty cycle when ENA is LOW. RP may be used as a read strobe for accessing data stored in a FIFO ...

Page 11

... DATA BOUNDARY CHANGES DATA DATA DATA RDY IS HIGH WHILE WAITING FOR K28.5 CY7B923 HOTLink Transmitter Operating Mode Description 12). Proper In normal operation, the transmitter can operate in either of two modes. The encoded mode allows a user to send and receive eight-bit data and control information without first converting it to transmission characters ...

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... Special Figure 6. Seamless FIFO Interface R Q ENR 0– SC/D ENN 0– SC/D CKR 0– CKW 0–8 CY7B923, CY7B933 = 111 00000 and SC/D = 7–0 CLOCKED FIFO 7C44X/5X Q CKR 0– SC/D CKW 0–7 7B923 HOTLink TRANSMITTER HOTLink RECEIVER 7B933 RDY Q , SC/D 0– ...

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... Transmitter Serial Data Characteristics The CY7B923 HOTLink transmitter serial output conforms to the requirements of the Fibre Channel specification. The serial data output is controlled by an internal PLL that multiplies the frequency of CKW maintain the proper bit clock frequency ...

Page 14

... D E CY7B933 Receiver 28 IB IB– IA IA– 0.01 F GND Fiber Optic PECL Load CY7B923, CY7B933 0.01 F VCC Fiber Optic Fiber Tx TX TX+ TX– GND Coax or Twisted Pair A B 270 270 0.01 F 649 1500 RL/2 Coax or Twisted Pair RL/2 Optional Signal Det ...

Page 15

... RVS output in the receiver. This can be done by explicitly sending a violation with the SVS input, or allowing the transmitter BIST loop to run while the receiver runs in normal mode. The BIST loop includes deliberate violation symbols and will adequately test the RVS function. CY7B923, CY7B933 OUTA OUTB OUTC SO ...

Page 16

... This function will allow system diagnostics to evaluate the error in an unambiguous manner, and will not require any modification to the receiver data interface for error-testing purposes. CY7B923, CY7B933 ), a context control bit (SC/D), and a system 7 = 111 00000 7–0 ...

Page 17

... Note Acquisition time is measured from worst-case phase or frequency change to zero phase and frequency error result of the receiver’s wide jitter tolerance, valid data appears at the receiver’s outputs a few byte times after a worst-case phase change. CY7B923, CY7B933 RVS SC/D Qouts Name 0 00-FFD0.0-31 00-0BC0 ...

Page 18

... The bit labeled A in the description of the 8B/10B Transmission Code corresponds to bit 0 in the numbering scheme of the FC-2 specification, B corresponds to bit 1, as shown below. FC-2 bit designation— HOTLink D/Q designation— 7 8B/10B bit designation— H CY7B923, CY7B933 , 0– ...

Page 19

... X3.230-199X ANSI FC-PH Standard). IBM Enterprise Systems Architecture/390 ESCON I/O Interface (document number SA22-7202). Document #: 38-02017 Rev. *H CY7B923, CY7B933 8B/10B Transmission Code The following information describes how the tables shall be used for both generating valid Transmission Characters (encoding) and checking the validity of received Transmission Characters (decoding) ...

Page 20

... Table 4 shows an example of this behavior. Character RD Character D21.1 – D10.2 101010 1001 – 010101 0101 101010 1011 + 010101 0101 D21.0 + D10.2 CY7B923, CY7B933 Table 3 Hex Value Character RD – D23.5 + – 111010 1010 + + 111010 1010 + + Code Violation ...

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... CY7B923, CY7B933 Page [+] Feedback ...

Page 22

... CY7B923, CY7B933 Page [+] Feedback ...

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... CY7B923, CY7B933 Page [+] Feedback ...

Page 24

... CY7B923, CY7B933 Page [+] Feedback ...

Page 25

... CY7B923, CY7B933 Page [+] Feedback ...

Page 26

... CY7B923, CY7B933 Page [+] Feedback ...

Page 27

... CY7B923, CY7B933 Page [+] Feedback ...

Page 28

... CY7B923, CY7B933 Page [+] Feedback ...

Page 29

... Code Rule Violation and SVS Tx Pattern 111 00000 100111 1000 111 00001 001111 1010 111 00010 110000 0101 Running Disparity Violation Pattern 111 00100 110111 0101 CY7B923, CY7B933 Current RD+ fghj abcdei fghj 110000 1011 110000 0110 110000 1010 110000 1100 110000 1101 110000 0101 110000 ...

Page 30

... Supply voltage to ground potential .............. –0 +7 input voltage .......................................... –0 +7.0 V Output current into TTL outputs (LOW) ....................... 30 mA Output current into PECL outputs (HIGH) ................. –50 mA CY7B923/CY7B933 Electrical Characteristics Parameter Description TTL OUTs, CY7B923: RP; CY7B933 Output HIGH voltage OHT V Output LOW voltage OLT ...

Page 31

... CY7B923/CY7B933 Electrical Characteristics Miscellaneous [11] I Transmitter power supply CCT current [12] I Receiver power supply CCR current Capacitance [13] Parameter Description C Input capacitance IN OUTPUT R1 = 910 510  < (Includes fixture and probe capacitance) (a) TTL AC Test Load 3.0V 3.0V 2.0V 1.0V GND < (c) TTL Input Test Waveform Notes 11 ...

Page 32

... CKW, but not RP function or timing pF. L 2.0V, over the operating range. CC /10 if data is being received. See note. CKW , SC/D, and RVS) are loaded with similar DC and AC loads. 07 CY7B923, CY7B933 7B923 7B923-400 Unit Min Max Min Max 30.3 62 ...

Page 33

... REFCLK clock pulse HIGH CPXH t REFCLK clock pulse LOW CPXL t Propagation delay (note PECL and TTL DS [26] thresholds) [13, 27] t Static alignment SA [13, 28] t Error-free window EFW Figure 10. Switching Waveforms for the CY7B923 HOTLink Transmitter CKW ENA D – SC/D, SVS, BISTEN RP CKW ENN D – ...

Page 34

... NOTE SO Static Alignment /2   INA ,  INB SAMPLE WINDOW Document #: 38-02017 Rev CPRH t CPRL t t PRH RH t PRF CKX t CPXH 1.5V Error-free Window /2   INA  INB CY7B923, CY7B933 t CKR t ROH t EFW t B BIT CENTER BIT CENTER Page [+] Feedback ...

Page 35

... DATA LATCHED IN CKW ENA D , 07 SC/D, DATA SVS RP  OUTX Ordering Information Package Speed Ordering Code Standard CY7B923-JC CY7B923-JXC CY7B923-JXCT CY7B923-JXI CY7B923-JXIT CY7B923-SXC CY7B923-SXCT 400 CY7B923-400JXC CY7B923-400JXCT Standard CY7B933-JC CY7B933-JXC CY7B933-JXCT CY7B933-JXI CY7B933-JXIT CY7B933-SXC CY7B933-SXCT 400 CY7B933-400JXC CY7B933-400JXCT Notes 29. C1.7 = Transmit Negative K28.5 (–K28.5+) disregarding Current RD. ...

Page 36

... Figure 13. 28-Pin Plastic Leaded Chip Carrier J64 Document #: 38-02017 Rev. *H Tape and reel Temperature range Commercial Industrial Package type PLCC PLCC (Pb-Free SOIC (Pb-Free) Base part number: 923 = Transmitter, 933 = Receiver Marketing Code HOTLink Transmitter/Receiver Company ID Cypress CY7B923, CY7B933 51-85001 *B Page [+] Feedback ...

Page 37

... Package Diagrams Figure 14. 28-Pin (300-Mil) Molded SOIC S21 Document #: 38-02017 Rev. *H CY7B923, CY7B933 51-85026 *E Page [+] Feedback ...

Page 38

... LPEN local loopback input PECL positive-ECL PLL phase-locked loop TTL transistor-transistor logic VCO voltage controlled oscillator Document #: 38-02017 Rev. *H CY7B923, CY7B933 Document Conventions Units of Measure Symbol Unit of Measure °C degrees Celsius MHz megahertz µA microamperes µs microseconds ...

Page 39

... Changed INA± pin description to include what to do with unused pairs of inputs. Changed Equation in note 6–old one made no sense. BSS Changed Hotlink Transmitter/Receiver to Hotlink Removed all references to Military parts (Obsolete): CY7B923-LMB, CY7B933-LMB KKV Minor change: reset Valid Data Characters (SC/D = LOW) table format to ...

Page 40

... Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-02017 Rev. *H ESCON is a registered trademark of IBM. HOTLink is a registered trademark of Cypress Semiconductor. All product and company names mentioned in this document may be the trademarks of their respective holders. cypress.com/go/plc Revised October 14, 2010 CY7B923, CY7B933 PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 ...

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