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... TECHNICAL MANUAL L80227 10BASE-T/ 100BASE-TX Ethernet PHY ® ...
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... LSI Logic does not assume any responsibility or liability arising out of the application or use of any product described herein, except as expressly agreed to in writing by LSI Logic; nor does the purchase or use of a product from LSI Logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of LSI Logic or third parties ...
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... Introduction, describes the device in general terms and Description, describes each of the internal Descriptions, lists and describes the device input Registers, gives a register summary and describes each Interface, describes the device Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. iii ...
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... Length and Type Least-Significant Bit Management Information Base Multi-Level Transmission (3 levels) millisecond Most-Significant Bit millivolt Normal Link Pulse Non-Return to Zero Inverted Non-Return to Zero Opcode Printed Circuit Board picofarad Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. ...
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... Registered Jack-45 Remote Monitoring Start Address or Station Address Start of Frame Delimiter Simple Network Management Protocol Start of Idle Start of Stream Delimiter Shielded Twisted Pair Twisted Pair microhenry microprocessor Unshielded Twisted Pair Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. v ...
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... Preface Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. ...
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... Descrambler Twisted-Pair Transmitters Twisted-Pair Receiver Clock and Data Recovery Link Integrity and AutoNegotiation Link Indication Collision LED Drivers 100 Mbits/s 10 Mbits/s Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. 1-1 1-3 2-2 2-3 2-3 2-3 2-8 2-8 2-9 ...
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... Status Register (Register 1) PHY ID 1 Register (Register 2) PHY ID 2 Register (Register 3) AutoNegotiation Advertisement Register (Register 4) AutoNegotiation Remote End Capability Register (Register 5) Configuration Register (Register 17) Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. 2-32 2-32 2-33 2-34 2-34 2-34 2-35 ...
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... Collision and JAM Timing Characteristics Link Pulse Timing Characteristics Jabber Timing Characteristics MI Serial Port Timing Characteristics L80227 Pinouts L80227 Pin Layout Clocks Output Drive Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. 4-17 5-1 5-2 5-4 5-5 6-1 6-2 ...
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... A.10 LED Drivers A.11 Power Supply Decoupling Customer Feedback x Contents MII Disable Receive Output Enable MII Based Repeaters Clocks Serial Port Addressing Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. A-10 A-11 A-11 A-11 A-11 A-12 A-12 A-14 A-15 ...
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... Typical Network Interface Adapter Card Schematic Using the L80227 A.2 Typical Switching Port Schematic Using L80227 A.3 Typical External PHY Schematic Using L80227 A.4 MII Output Driver Characteristics Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. 1-2 2-4 2-5 2-6 2-17 2-19 2-23 ...
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... A.5 Serial Device Port Address Selection A.6 Connecting the L80227 to a High-Capacitance Crystal A.7 Connecting the L80227 to a Non High-Capacitance Crystal A-14 xii Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. A-13 A-14 ...
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... L80227 Pin List (by Signal Category) 6.14 L80227 Pin List (by Pin Number) A.1 TP Transformer Specification A.2 TP Transformer Sources A.3 Non High-Capacitance Crystal Specifications Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. 2-2 2-6 2-7 2-10 2-17 2-29 2-29 2-30 ...
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... Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. ...
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... The PHY channel contains the following blocks: 4B5B Encoder/Manchester Encoder Scrambler 10BASE-T Transmitter 100BASE-TX Transmitter 10BASE-T Receiver 100BASE-TX Receiver Squelch Clock and Data Recovery Link Integrity and Autonegotiation L80227 10BASE-T/100BASE-TX Ethernet PHY Technical Manual Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. 1-1 ...
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... Transmitter Manchester 10BASE-T Transmitter Encoder Squelch 4B5B Clock & Data Descrambler Decoder Recovery Auto- Negotiation and Link Squelch Clock & Data Recovery (Manchester Decoder) Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. L80227 TP Interface 100BASE-TX Receiver 10BASE-T Receiver ...
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... On-chip wave shaping (no external filters required) Adaptive equalizer for 100BASE-TX operation Baseline wander correction Minimum number of external components LEDs are individually programmable to reflect any the following events: – Features Link Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. 1-3 ...
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... V power supply tolerant I/O 64-pin LQFP Operating temperature ranges available: – – 1-4 Introduction Activity Collision Full-Duplex 10/100 Mbits/s Commercial (L80227): 0˚ to +70˚ C Industrial (L80227 I): -40˚ to +85˚ C Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. ...
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... Section 2.6, “Full-/Half-Duplex Mode” Section 2.7, “10/100 Mbits/s Selection” Section 2.8, “Jabber” Section 2.9, “Reset” Section 2.10, “Receive Polarity Correction” L80227 10BASE-T/100BASE-TX Ethernet PHY Technical Manual Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. 2-1 ...
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... Device Differences This manual describes the L80227 PHY similar to the L80223 and L80225 PHY devices. Each of these devices is similar with respect to Ethernet operation. devices. Table 2.1 Function Power Supply RESET Pin FX Interface Transmit Transformer Winding Ratio Speed Pin Duplex Pin Hardware Advertisement Control Registers 16 – ...
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... Controller Interface. Overview Figure 2.1. Unless otherwise noted, the operation and specifications for the industrial temperature devices are identical to the commercial temperature range device. Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. 2-3 ...
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Figure 2.1 L80227 Device Block Diagram OSCIN Oscillator RESETn RX_EN TX_CLK TXD[3:0] TX_EN TX_ER COL Controller Collision Interface (MII) RX_CLK RXD[3:0] CRS RX_DV RX_ER MDC Serial MDIO Port (MI) LED[3:0]n LED MDA[3:0]n Drivers 100BASE-TX Transmitter 4B5B MLT3 Scrambler Encoder Encoder ...
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... Base-T Data Symbols SFD NoTransitions ] IDLE = [ ...] 62 Bits Long PREAMBLE = [ SFD = [ DATA ] [ With No MID Bit SOI = Transition Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. Interframe LLC Data Gap LN FCS LN LLC DATA FCS ESD Before/After 4B5B Encoding, Scrambling, and MLT3 Coding ...
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... DATA N-1 DATA N 2 Bits [ ...] 62 Bits Long SFD = [ DATAn = [Between 64 1518 Data Bytes] IDLE = TX_EN = 0 b. MII Nibble Order MAC Serial Bit Stream Bit Value Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. TX_EN = 0 IDLE MSB Second Nibble ...
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... AutoNegotiation algorithm Overview Table 2.3. Bit Value Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved ...
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... The device provides either a 2.5 MHz or 25 MHz reference clock at the TX_CLK or RX_CLK output pins for 10-MHz or 100 MHz operation, respectively. 2-8 Functional Description shows the main blocks, along with their associated signals. Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. Figure 2.1. The ...
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... Receive data bits (RXD[3:0]) Receive clock (RX_CLK) Carrier sense (CRS) Receive data valid (RX_DV) Receive data error (RX_ER) Collision (COL). Block Diagram Description Figure 2.3. The L80227 meets all Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. 2-9 ...
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... Data 6 7 Data 7 8 Data 8 9 Data 9 A Data A B Data B C Data C D Data D Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. Table 2.4. 5B Code 4B Code 0b11110 0b0000 0b01001 0b0001 0b10100 0b0010 0b10101 0b0011 0b01010 0b0100 0b01011 ...
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... RX_CLK for the duration of that RX_CLK clock cycle during which the nibble containing the error is output on RXD[3:0]. The collision output, COL, is asserted whenever the collision condition is detected. Block Diagram Description Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. 5B Code 4B Code 0b11100 0b1110 ...
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... This section describes the 4B5B encoder, which is used in 100 Mbits/s operation. It also describes the Manchester Encoder, used in 10BASE-T operation. 2-12 Functional Description 2.3. When the end of packet is detected, CRS and RX_DV Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. ...
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... Figure 2.1 2.2. The 4B5B encoder also fills the period between packets Figure 2.1 Figure 2.2. The Manchester encoding process is only done Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. converts the four-bit data Table 2.4. Table 2.4, and ...
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... IEEE 802.3 specifications, aligns the data on the correct 5B word boundaries, and sends it to the 4B5B decoder. 2-14 Functional Description Table 2.4, and sends the 4B nibbles to the Figure 2.1 is used in Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. Figure 2.2). ...
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... IEEE 802.3. The waveform generator eliminates the need for any external filters on the TP transmit output. Block Diagram Description Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. 2-15 ...
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... During the idle period, no output signals are transmitted on the TP outputs except for link pulses. 2-16 Functional Description Figure 2.1). Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. Figure 2.4. The ...
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... T Table 2.5 Reference Block Diagram Description Time (ns) TP Output Voltage (10 Mbits/s) Time (ns) Internal MAU Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved 100 110 Voltage (V) 0 1.0 0.4 0.55 0.45 0 1.0 0.7 0.6 0 0.55 0.55 2-17 ...
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... Functional Description TP Output Voltage (10 Mbits/s) (Cont.) Time (ns) Internal MAU 100 P 110 Q 111 R 108 S 111 T 110 U 100 V 110 W 90 Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. Voltage (V) 0 1.0 0.4 0.75 0.15 0 0.15 1.0 0.3 0.7 0.7 ...
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... Short Bit Slope 0.5 V/ns 585 mV sin ( t/PW Long Bit Slope 0.5 V/ns 585 mV sin ( t/PW) 585 mV sin[2 (t PW2)/PW)] 3PW/4 PW Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. Figure 2.5. The TP inputs are 3.1 V 585 mV 3.1 V 585 mV 2-19 ...
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... Mbits/s mode for that purpose) start of packet is determined when the receiver goes into the unsquelch state and CRS is asserted the receiver meets the squelch requirements defined in IEEE 802.3 Clause 14. 2-20 Functional Description Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. ...
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... The data recovery process for 10 Mbits/s mode is identical to that of the 100 Mbits/s mode. As mentioned in the Manchester Decoder section, the data recovery process inherently performs decoding of Manchester encoded data from the TP inputs. Block Diagram Description Figure 2.3 Figure 2.3. Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. 2-21 ...
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... Link Pass state). The transmit link pulse meets the template requirements defined in IEEE 802.3 and shown in details if needed. 2-22 Functional Description Figure 2.6. Refer to IEEE 802.3 for more Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. ...
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... The transmit FLP pulses meet Block Diagram Description Link Pulse Output Voltage Template (10 Mbits/s) 1 0.5 V/ns 0.5 BT 0.6 BT 2.0 BT 300 mV 200 mV 0.25 BT 3.1 V 0.85 BT 2.0 BT Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. 4 4.0 BT 42.0 BT 2-23 ...
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... NLP vs FLP Link Pulse Normal Link Pulse (NLP) Fast Link Pulse (FLP D14 D15 Clock Clock Clock Clock Clock Clock Clock Data Data Data Data Data Data Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. Figure 2.6. A timing Figure 2.7. ...
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... Mbits/s mode is determined with the state of the SPEED bit in the MI serial port Control register and the half- or full-duplex mode is determined with the state of the DPLX bit in the MI serial port Control register. Block Diagram Description Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. 2-25 ...
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... TPO+/-) and reception (non-idle symbols detected at the TP+/- input). When a 2-26 Functional Description . The PLED0n output has both pullup and DD or GND. Both the PLED3n and PLED0n DD Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. for more details on how to ...
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... PLED2n output. Set the PLED2_[1:0] bits in the same register to 0b11 (normal). With these settings, an LED connected to the PLED2n pin will reflect collision activity. Block Diagram Description Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. 2-27 ...
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... PLED0_[1:0] control the PLED0n output The PLEDn_[1:0] bits program the outputs to operate in the following modes: 2-28 Functional Description . The PLED[1:0]n outputs have both pullup and DD or GND. DD Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. for more details on how to ...
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... Table 2.8. PLED4n PLED3n XMT ACT LINK XMT ACT LINK XMT ACT LINK + ACT XMT ACT LINK 100 Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. PLED2n PLED1n PLED0n COL FDX 10/100 ACT FDX 10/100 COL FDX 10/100 ...
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... Activity occurred; stretch pulse to 100 ms 100 Mbit/s link detected Collision occurred; stretch pulse to 100 ms Full-Duplex mode enabled 10 Mbits/s mode enabled (HIGH), or 100 Mbits/s mode enabled (LOW) 10 Mbits/s link detected 2.2. Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. Table 2.4 Figure 2.2. ...
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... End of Packet This section describes end of packet operation for both the 100 Mbits/s and 10 Mbits/s modes. End of Packet 2-9. See Section 2.3.8.4, “Squelch (10 for details on the squelch algorithm. Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. Section 2-31 ...
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... SOI output pulse at the TP output to meet the pulse template requirements specified in IEEE 802.3 Clause 14 and shown in 2-32 Functional Description Table 2.4 and Figure 2.2. Figure 2.8. Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. ...
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... The collision function is disabled, and TX_EN to CRS loopback is disabled Full-/Half-Duplex Mode SOI Output Voltage Template (10 Mbits/s) 4 3.1 V 0.5 V/ns 0.25 BT 2.25 BT 6.0 BT 585 mV (t/1 BT)) 2.5 BT 3.1 V 2.5 BT 4.5 BT Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved 45.0 BT 2-33 ...
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... TX_EN is internally looped back onto CRS during every transmit packet. This internal CRS loopback is disabled during collision, in Full-Duplex 2-34 Functional Description AutoNegotiation”. or GND and can also drive a digital input. DD Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. Section for more details on how to ...
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... AutoNegotiation. Appropriately setting the bits in the MI serial port AutoNegotiation Advertisement register selects the advertised speed capability. AutoNegotiation functionality is described in more detail in Section 2.3.10, “Link Integrity and 10/100 Mbits/s Selection AutoNegotiation”. Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. 2-35 ...
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... When reset occurs because of (1) or (2), an internal power-on reset pulse is generated that resets all internal circuits, forces the MI serial port 2-36 Functional Description or GND and can also drive a digital input applied to the device, or Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. for more details on how to ...
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... To disable autopolarity, set the Autopolarity Disable bit (APOL_DIS) in the MI serial port Configuration register. No polarity detection or correction is needed in the 100 Mbits/s mode. Receive Polarity Correction Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. . The device is DD 2-37 ...
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... Functional Description Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. ...
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... Section 3.3, “Management Interface (MI)/LED Signals” Section 3.4, “LED Signals” Section 3.5, “Miscellaneous Signals” Section 3.6, “Power Supply” Figure 3 logic diagram for the device. L80227 10BASE-T/100BASE-TX Ethernet PHY Technical Manual Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. 3-1 ...
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... Twisted-Pair Transmit Output (Positive) The TPO+ pin functions as the positive signal in the twisted-pair output. Twisted-Pair Transmit Output (Negative) The TPO- pin functions as the negative signal in the twisted-pair output. Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. LEDs/ MI Address Miscellaneous I O ...
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... When RX_EN is LOW, the outputs are in a high-imped- ance state. Receive Error Output RX_ER is asserted HIGH when a coding error or other specified errors are detected on the receive twisted-pair inputs. The signal is clocked out on the falling edge of RX_CLK. Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved ...
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... The default function of this pin 100 Mbits/s Link Detect output. This pin can also be programmed through the MI serial port to indicate other events or be user con- trolled. This pin can drive an LED from V Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved ...
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... This pin can drive an LED from both V GND. When programmed as Full Duplex Detect Output (default): Pin Function HIGH Half-Duplex LOW Full-Duplex Management Interface (MI)/LED Signals Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. Pullup O.D. I Pullup O.D. I/O and DD 3-5 ...
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... The function of this pin Transmit Activity Detect output. This pin can also drive an LED from V HIGH = No Transmit Activity LOW = Transmit packet occurred: hold LOW for 100 ms Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. Pullup O.D. I/O and GND. DD Pullup O ...
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... These pins are reserved for future use and should be left floating for proper operation. Hardware Reset Input Pin Meaning HIGH Normal LOW Device in reset state. Reset is finished 100 ms after RESETn goes HIGH. Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved Pullup I 3-7 ...
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... Speed Select bit (SPEED) in the MI serial port Control register or the AutoNegotiation outcome. Ground The ground pins must be connected to ground (0 Volts). Positive Supply The V pins must be connected to 3.3 DD Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved Volts. ...
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... LOW until read. After they are read, they are reset HIGH. R/LH bits are the same as R/LL bits, except that they latch HIGH. L80227 10BASE-T/100BASE-TX Ethernet PHY Technical Manual Table 4.1: Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. 4-1 ...
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... No operation, Hi-Z Output When the bit goes HIGH latched. When the bit Is read updated. No operation, Hi-Z Output When the bit transitions, the bit is latched. When the bit is read, the bit is updated. Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. ...
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... ANEG_EN PDN Reserved CAP_TF CAP_TH REM_FLT CAP_ANEG OUI6 OUI7 OUI14 OUI15 OUI22 OUI23 PART0 REV3 Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved MII_DIS ANEG_RST DPLX Reserved LINK JAB EXREG OUI8 OUI9 OUI10 OUI16 OUI17 OUI18 OUI24 PART5 ...
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... Status Output Register (Register 18 Reserved 4-4 Registers Reserved 5 4 Reserved Reserved 5 4 Reserved PLED2_0 PLED1_1 4 3 JAB_DIS MREG Reserved SPD_DET DPLX_DET Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved TX_FDX 1 0 CSMA TX_FDX 1 0 CSMA PLED1_0 PLED0_1 PLED0_0 Reserved Reserved ...
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... Mbit/s (100BASE-TX) (default Mbit/s (10BASE-T) 1. The SPEED bit is effective only when AutoNegotiation is off AutoNegotiation Enable Bit Meaning AutoNegotiation enabled (default Disabled Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved MII_DIS ANEG_RST DPLX 0 R/WSC 15 R/W 14 R/W 13 R/W 12 4-5 ...
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... Collision Test Enable Bit Meaning 1 Collision test enabled 0 Normal (default) Reserved These bits are reserved and must remain at the default value of 0x00 for proper device operation. Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. R/W 11 R/W 10 R/WSC 9 R [6:0] ...
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... Bit Meaning 1 Capable of 10BASE-T Full-Duplex (default) 0 Not capable of 10BASE-T Full-Duplex 10BASE-T Half Duplex Capable Bit Meaning 1 Capable of 10BASE-T Half Duplex (default) 0 Not capable of 10BASE-T Half Duplex Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved Reserved LINK JAB EXREG ...
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... Fault (RF) bit is set in the AutoNegotiation Remote End Capability register remote fault (default) AutoNegotiation Capable Bit Meaning 1 Capable of AutoNegotiation (default) 0 Not capable of AutoNegotiation Link Status Bit Meaning 1 Link detected. 0 Link not detected (default) Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. R [10: R/ R/LL 2 ...
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... Bit OIU24 OIU23 OIU22 OIU21 OIU20 OIU19 OIU18 OIU17 OIU16 OIU15 OIU14 OIU13 OIU12 OIU11 OIU10 OIU9 Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved OUI8 OUI9 OUI10 2 1 OUI16 OUI17 OUI18 R [15:0] Default Value Hex Value 0 0x7 1 ...
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... PART[5:0] field: Bit PART[5] PART[4] PART[3] PART[2] PART[1] PART[0] Manufacturer’s Revision Number The default value for this field is 0x0. Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. Default Value Hex Value 0 0x0 0x0 ...
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... Reserved These bits are reserved and must remain at the default value of 0b00 for proper device operation 100BASE-T4 Capable Bit Meaning 1 Capable of 100BASE-T4 operation 0 Not capable (default) Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved TX_FDX 1 0 CSMA R 15 ...
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... These bits are reserved and must remain at the default value of 0x0 for proper device operation CSMA 802.3 Capable Bit Meaning 1 Capable of 802.3 CSMA 0 Not capable 1. Carrier-Sense, Multiple-Access Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. R/W 8 R/W 7 R/W 6 R/W 5 R/W [4:1] R operation (default) ...
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... Reserved These bits are reserved and must remain at the default value of 0b00 for proper device operation 100BASE-T4 Capable Bit Meaning 1 Capable of 100BASE-T4 operation 0 Not capable (default) Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved TX_FDX 1 0 CSMA R 15 ...
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... Reserved These bits are reserved and must remain at the default value of 0x0 for proper device operation CSMA 802.3 Capable Bit Meaning 1 Capable of 802.3 CSMA 0 Not capable (default) 1. Carrier-Sense, Multiple-Access Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved [4: Operation ...
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... PLED2_1n PLED2_0n Meaning Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved PLED1_0n PLED0_1n PLED0_0n 2 1 Reserved R/W [15:14] Normal: PLED3n pin state is determined from the LED_DEF[1:0] bits (default is LINK100). 0b11 is the default for these bits LED tied to PLED3n blinks (toggles 100 ...
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... HIGH) LED Normal Function Select See Table 2.7 on page 2-29 Autopolarity Disable Bit Meaning 1 Autopolarity correction disabled 0 Normal (default) Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. R/W [11:10] R/W [9:8] R/W [7:6] for these bit definitions ...
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... Device Mbits/s mode (10 BASE-T) Duplex Detect Bit Meaning 1 Device is operating in Full-Duplex 0 Device is operating in Half-Duplex Reserved These bits are reserved and must remain at the default value of 0x0 for proper device operation. Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved [2: [5:0] 4-17 ...
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... Registers Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. ...
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... MI serial port. When an MI read or write cycle occurs, the device compares the internally inverted and latched state of the MDA[4:0]n pins to the L80227 10BASE-T/100BASE-TX Ethernet PHY Technical Manual Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. 5-1 ...
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... MDIO output driver goes into a high-impedance state. Another serial shift cycle cannot be initiated until the idle condition is detected again (at least 32 continuous 1s). diagram for a MI serial port cycle. 5-2 Management Interface Figure 5.1 Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. shows a timing ...
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... MDC MDIO PHYAD WRITE Bits PHY clocks in data on rising edges of MDC with minimum, and t s Note start bits operation bits (read or write), PHAD = PHY address, REGAD = register address turnaround bits For more detailed information on the timing related D15 D14 D13 D12 D11 ...
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... Start Bits When ST[1: serial port access cycle starts. Read Select When the READ bit designates a read cycle. Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. Figure 5.2 and a timing are start bits (ST[1:0]) and shows the MI frame structure. ...
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... These 16 bits contain data to or from one of the registers selected with the register address bits REGAD[4:0]. Summary”. See for a complete description of each register. Table 5.1 Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved Chapter 4, gives a summary of the functions W ...
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... Contain an identification code unique to the device Contains bits that control the operation of the AutoNegotiation algorithm Contains bits that reflect the AutoNegotiation capabilities of the link partner’s PHY Stores various configuration bits Contains status Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. ...
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... Lead Temperature (soldering, 10 sec) Body Temperature (soldering, 30 sec) L80227 10BASE-T/100BASE-TX Ethernet PHY Technical Manual shows the device absolute maximum ratings. These are limits Absolute Maximum Ratings Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. Range Units 0.3V to +4.0V V ...
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... V 200 DD 2 120 150 1 150 0.4 1 Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. Unit Conditions Volt All except OSCIN, MDA[3:0]n Volt MDA[3:0]n Volt OSCIN Volt All except OSCIN, MDA[3:0]n mV MDA[3:0]n Volt OSCIN A VIN=GND. All except OSCIN, ...
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... Figure A.1 shows the twisted-pair characteristics for transmit operation. Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. Unit Conditions Volt IOH = 4 mA. All Except PLED[5:0]n Volt IOH = 4 A. PLED[5:2]n Volt IOH = 10mA. PLED[1:0]n ...
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... Mbits/s 0.80 1 Ohm 15 pF Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. Conditions 100 Mbits/s, UTP mode, 100 ohm load 10 Mbits/s, UTP mode, 100 ohm load 100 Mbits/s, ratio of positive and negative amplitude peaks on TPO 100 Mbits/s ...
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... V 2.4 DD 0.2 R 0.25 OCV Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. Unit Conditions mV pk 100 Mbits/s, RLVL = Mbits/s, RLVL = 100 Mbits/s, RLVL = Mbits/s, RLVL = 0 Volt Voltage on either TPI+ or TPI with respect to GND. Voltage on TPI with respect to GND. ...
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... All other inputs and outputs 6-6 Specifications Parameter Value + - MHz 0.01% REXT 10K 1%, no load tr ns, 20-80% points Same Figure A.1 1K pullup equivalent 25 pF 0.0 V during data, 0 start/end of packet 1.4 V Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. Table 6.5. ...
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... Transmit AC timing parameters. See for the 100 Mbits/s and 10 Mbits/s transmit timing diagrams. Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. Unit Conditions ns Clock applied to OSCIN ns Clock applied to OSCIN ns Clock applied to OSCIN ns 100 Mbits/s ...
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... Deassert 250 4500 80 Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. Unit Conditions ns 100 Mbits Mbits 100 Mbits/s 240 ns 10 Mbits 100 Mbits/s 240 ns 10 Mbits Note ...
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... Figure 6.2 Transmit Timing (100 Mbits/s) MI 100 Mbits/s TX_CLK t 15 TX_EN t 17 CRS TXD[3: TX_ER t 23 TPO IDLE FXO t 27 PLEDn AC Electrical Characteristics IDLE /J/ Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved DATA /T/R/ IDLE 6-9 ...
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... Figure 6.3 Transmit Timing (10 Mbits/ Mbits/s TX_CLK t 15 TX_EN t 17 CRS TXD[3: TP0 t 27 PLEDn 6-10 Specifications PREAMBLE PREAMBLE t 28 Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved DATA DATA SOI ...
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... Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. Figure 6.4 Unit Conditions ns 100 Mbits/s, MII ns 10 Mbits/s ns 100 Mbits/s, MII ns 10 Mbits/s. relative to start of SOI pulse ns 100 Mbits Mbits/s ns 100 Mbits Mbits/s ...
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... RX_EN Assert to Rcv MII Output Active Delay 6-12 Specifications Limit Min Typ Max 3.0 13 105 Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. Unit Conditions 100 Mbits -pk 10 Mbits/s ms PLEDn Programmed for Activity ms PLEDn Programmed for Activity ...
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... TPI DATA FXI CRS RX_CLK RX RX RX_DV RXD[3:0] DATA DATA AC Electrical Characteristics DATA DATA DATA DATA Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. DATA DATA DATA DATA DATA DATA PREAMBLE PREAMBLE PREAMBLE PREAMBLE PREAMBLE DATA RX I 6-13 ...
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... Figure 6.6 Receive Timing, Start of Packet (10 Mbits/ Mbits/s TPI t 31 CRS RX_CLK TX TX RX_DV RXD[3:0] RX_ER t 43 PLEDn 6-14 Specifications Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved DATA DATA DATA PREAMBLE PREAMBLE DATA RX DATA ...
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... DATA DATA DATA DATA CRS RX_CLK RX RX RX_DV RXD[3:0] DATA DATA Figure 6.8 RX_EN Timing RX_EN t RX_CLK 46 RXD[3:0] RX_DV RX_ER COL AC Electrical Characteristics SOI DATA DATA DATA DATA Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved DATA 6-15 ...
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... Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. Conditions 100 Mbits/s 10 Mbits/s 100 Mbits/s 10 Mbits/s 100 Mbits/s 10 Mbits/s 100 Mbits/s 10 Mbits/s PLEDn Programmed for Collision PLEDn Programmed for Collision 100 Mbits/s 10 Mbits/s ...
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... PLEDn Figure 6.10 Collision Timing, Receive (10 Mbits/ Mbits/s TPO TPI COL PLEDn AC Electrical Characteristics DATA DATA DATA DATA DATA DATA DATA Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. DATA DATA DATA DATA DATA DATA DATA DATA I 6-17 ...
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... TPI TPO COL PLEDn Figure 6.13 Collision Test Timing TX_EN t 57 COL 6-18 Specifications DATA DATA DATA DATA DATA DATA DATA Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. DATA DATA DATA DATA DATA DATA DATA DATA I ...
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... Link Pulse AC timing parameters. See for the Link Pulse timing diagrams. Limit Min Typ See Figure 2 100 55.5 62.5 111 125 Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. Figure 6.14 Max Unit Condition link_test_min 150 ms link_test_max 3 Link lc_max Pulses 150 ns 69 ...
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... Min Typ Max 165 185 100 150 1200 1500 1200 1500 750 1000 Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. Unit Condition ms flp_test_max_timer ms data_detect_min_ timer ms data_detect_max_ timer Link Pulses ms nlp_test_min_timer ms nlp_test_max_ timer Link Pulse ms ms break_link_timer ms link_fail_inhibit_ ...
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... Min Typ Max 165 185 100 150 1200 1500 1200 1500 750 1000 Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. Unit Condition ms flp_test_max_timer ms data_detect_min_ timer ms data_detect_max_ timer Link Pulses ms nlp_test_min_timer ms nlp_test_max_ timer Link Pulse ms ms break_link_timer ms link_fail_inhibit_ ...
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... Min Typ Max 165 185 100 150 1200 1500 1200 1500 750 1000 Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. Unit Condition ms flp_test_max_timer ms data_detect_min_ timer ms data_detect_max_ timer Link Pulses ms nlp_test_min_timer ms nlp_test_max_ timer Link Pulse ms ms break_link_timer ms link_fail_inhibit_ ...
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... Figure 6.14 NLP Link Pulse Timing a. Transmit NLP TPO TPI PLEDn AC Electrical Characteristics Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved Receive NLP 6-23 ...
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... LEDn 6-24 Specifications a. Transmit FLP and Transmit FLP Burst CLK DATA CLK DATA Receive FLP CLK DATA t 31.25 62. Receive FLP Burst Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. CLK CLK DATA CLK DATA 93.75 125.00 156. ...
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... MI 10 Mbits/s TXEN TPO COL CRS AC Electrical Characteristics shows the Jabber AC timing parameters. See Limit Min Typ 50 250 Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. Figure 6.16 for Max Unit Conditions 100 ms 10 Mbits/s 750 ms 10 Mbits 6-25 ...
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... TA0 D15 REGAD0 TA1 REGAD0 TA1 TA0 D15 Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. Unit Conditions Write Bits ns Write Bits ns Read Bits ns Write-Read Bit Transition ns Read-Write Bit Transition Clocks Number of consecutive MDC clocks with MDIO = 1 ...
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... Receive Data Valid Output Receive Enable Input Receive Error Output Receive Data Output Receive Data Output Receive Data Output Receive Data Output Transmit Clock Output Transmit Enable Input Transmit Error Input Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. 6-27 ...
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... Programmable LED Output/Management Interface Address Input Transmit LED Output Receive LED Output AutoNegotiation Control Input Collision Output Full/Half-Duplex Select Input Speed Select Input No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. ...
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... No Connect No Connect Reset Input Positive Supply. 3 Volts Positive Supply. 3 Volts Positive Supply. 3 Volts Positive Supply. 3 Volts Positive Supply. 3 Volts Positive Supply. 3 Volts Ground Ground Ground Ground Ground Ground Ground Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. 6-29 ...
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... Management Interface (MI) Data Input/Output Collision Output Carrier Sense Output Receive Data Valid Output No Connect No Connect No Connect Receive Error Output Receive Data Output Receive Data Output Receive Data Output Receive Data Output Ground No Connect Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. ...
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... Transmit Data Input Transmit Data Input Transmit Data Input Transmit Data Input Transmit Error Input Transmit Enable Input Ground Clock Oscillator Input No Connect Reset Input No Connect No Connect No Connect No Connect No Connect Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. 6-31 ...
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... Positive Supply. 3 Volts Twisted Pair Receive Input, Positive Twisted Pair Receive Input, Negative Ground Programmable LED Output/Management Interface Address Input Programmable LED Output/Management Interface Address Input Receive LED Output No Connect Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. ...
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... MDC 10 MDIO 11 COL 12 CRS 13 RX_DV pins are not connected. Pinouts and Package Drawings shows the pin layout for the L80227 package. L80227 64-Pin LQFP Top View Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved RESETn OSCIN 41 GND4 40 TX_EN 39 ...
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... Specifications ccc A See Detail A E Dimension Table Detail A Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. Symbol Dimensions b 0.17 - 0.27 e 0.50 Basic ccc Max. 0.08 ddd Max. 0.08 D 11.85 - 12.15 E 11.85 - 12.15 L 0.45 - 0.75 L1 1.0 Ref R 0 ...
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... A typical example schematic of the L80227 used in an network interface adapter card application is shown in application is shown in shown in L80227 10BASE-T/100BASE-TX Ethernet PHY Technical Manual Figure Figure A.2; and an external PHY application is Figure A.3. Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. A.1; a typical switching port A-1 ...
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... TPO TX_D1 TX_D0 TX_EN TX_ER TPO COL RX_CLK RXD3 RXD2 RXD1 RXD0 CRS 25 RX_DV 1% RX_ER TPI MDC 25 MDIO 1% L80227 RX_EN 25 RESETn 1% TPI PLED[5:0]n REXT OSCIN GND [6:1] Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved 1:1 1 RJ45 1 0.01 0. ...
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... TPO TX_ER COL RX_CLK RXD3 RXD2 RXD1 RXD0 25 CRS 1% RX_DV RX_ER TPI MDC 25 MDIO 1% L80227 0.01 RX_EN 25 RESETn 1% TPI 25 1% PLED[5:2]n REXT PLED[1:0]n OSCIN GND [6:1] Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. 1:1 1 RJ45 1 0. A-3 ...
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... TXD0 TX_EN TPO TX_ER COL RX_CLK RXD3 RXD2 RXD1 25 RXD0 1% CRS TPI RX_DV 25 RX_ER 1% MDC MDIO L80227 25 1% RX_EN TPI RESETn 25 1% REXT PLED[5:0]n 1% OSCIN GND [6:1] Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved 1 1 0.01 0. RJ45 ...
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... CT 0.05–0.15 Max) TP Transformer Sources Part Number H1089, H1102 S558-5999-J9, 558-5999-46 TG22-3506ND TG110-S050N2 EPF8017GH mod2 technology 0510 TM Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. Figure A. shown in Figure A.1 DD Table A.2. Specification Receive 1:1 350 350 0.0– ...
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... A.3. Figure A.1 through Figure Table A.1 and sources for the transformer are Table A.2. Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. Figure A.1 Table A.2 all contain through Figure A.3. common- Figure A.1 A.3. The specifications for this Figure A ...
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... Mbits/s, STP) = 100 mA (10 Mbits/s, UTP) = 81.6 mA (10 Mbits/s, STP) 1% resistor to meet IEEE 802.3 is then automatically changed inside ref Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. Figure A.1 through Table A.2 all contain through Figure A ...
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... L80227 this, use OSCIN as A-8 Application Information s mode or UTP120/STP150 modes are its/ causes droop to appear at the transmit interface to the TP Table A.1, the transmit interface to the TP cable then through Figure A.3. Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. Figure A.1 through ...
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... Figure A.2), these terminations resistors are not needed. MII Controller Interface 1% termination resistors are added. These termination Figure A.3. If the L80227 is used in embedded applications, Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. Figure A.4 if Figure A.1 and A-9 ...
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... MII bus, such as in the use of hubs, so the device powers up with the MII interface enabled. A-10 Application Information Voh Vol Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved Rol = 40 ohm min 3 lol ...
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... TX_CLK output clock. It may be desirable or necessary in some repeater applications to clock in the transmit data from a master Repeater Applications Section A.6.4, “Receive Output for more details about RX_EN. Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. A-11 ...
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... PLED[1:0]n outputs can drive LEDs tied to either V A-12 Application Information Figure A.3. Figure . The PLED[1:0]n outputs have both pullup and DD Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. Figure A.1 A.5a. At powerup or reset, the or GND. DD ...
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... PLED[3:0]n c. Setting Address without LEDs High Low Tie Serial Port Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. A.4b. To set an address bit HIGH, the resistor to GND must be A.4c. To set an address bit HIGH, the resistor to GND. 500 PLED[3:0]n 50K ...
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... A-14 Application Information Figure Connecting the L80227 to a High-Capacitance Crystal OSCIN L80227 Connecting the L80227 to a Non High-Capacitance Crystal OSCIN L80227 Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. A.6. Figure A.7. ...
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... A.3. The PLED[1:0]n outputs can drive LEDs or GND. DD pins on the L80227 and seven GND pins. DD pins should be connected together as closely as possible to DD plane. If the V DD Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. 0.01% max as shown in DD pins vary in potential by DD pins should DD ...
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... Figure A.3 has to be well decoupled to minimize and the GND plane. This decoupling DD pins should be within 50 mV p-p of each other DD Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. /GND set, one 0 /GND set DD ...
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... Please include your name, phone number, fax number, and company address so that we may contact you directly for clarification or additional information. Thank you for your help in improving the quality of our documents. L80227 10BASE-T/100BASE-TX Ethernet PHY Technical Manual Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. ...
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