SLXT973QCA3V 856775 Intel, SLXT973QCA3V 856775 Datasheet - Page 17

• Manufacturer Part Number: SLXT973QCA3V 856775
• Manufacturer: Intel

Specifications of SLXT973QCA3V 856775

• Lead Free Status / RoHS Status: Not Compliant

Datasheet
Document #: 249426
Revision #: 002
Rev. Date: March 1, 2002
Table 2. LXT973 Port 0 Signal Descriptions (Continued)
Table 3. LXT973 Port 1 Signal Descriptions
20
26
25
2
1
100
99
98
94
97
85
86
87
88
89
93
92
Pin #
1. AI = Analog Input, AO = Analog Output, I = Input, O = Output, OD = Open Drain output,
1. AI = Analog Input, AO = Analog Output, I = Input, O = Output, OD = Open Drain output,
Pin #
ST = Schmitt Triggered input, TS = Tri-State-able output, SL = Slew-rate Limited output,
IP = Weak Internal Pull-up, ID = Weak Internal Pull-down.
ST = Schmitt Triggered input, TS = Tri-State-able output, SL = Slew-rate Limited output,
IP = Weak Internal Pull-up, ID = Weak Internal Pull-Down
Signal Names
MDDIS0
MDC0
MDIO0
TXD1_3
TXD1_2
TXD1_1
TXD1_0
TXEN1
TXER1
TXCLK1
RXD1_3
RXD1_2
RXD1_1
RXD1_0
RXDV1
RXER1
RXCLK1
Signal Names
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
Type
I/O
Type
O, TS
O, TS
O, TS
O, TS
O, TS
I
I
1
I
I
I
1
Management Disable. When MDDIS0 is tied High, the MDIO port is
completely disabled and the Hardware Control Interface pins set their
respective bits at power-up and reset.
When MDDIS0 is pulled Low at power-up or reset via the internal pull-
down resistor or by tying it to ground, the Hardware Control Interface
Pins control only the initial or “default” values of their respective register
bits. After the power-up/reset cycle is complete, bit control reverts to the
MDIO serial channel.
Management Data Clock. Clock for MDIO0 serial channel. Maximum
frequency is 20 MHz.
Management Data Input/Output. Bi-directional serial data channel for
PHY/STA communication.
Transmit Data. TXD1_n is a bundle of parallel data signals driven by
the MAC controller. TXD1<3:0> transition synchronously with respect
to the TXCLK1. TXD1<0> is the least significant bit. In normal mode,
only TXD1<3:0> are monitored.
Transmit Enable. The MAC asserts TXEN1 when it drives data on
TXD0n. This signal must be synchronized to TXCLK1.
Transmit Error. (TXER1 is a 100 Mbps only signal.) The MAC asserts
this input when an error has occurred in the transmit data stream.
When operating at 100 Mbps, the LXT973 responds by sending "H
Symbols" on the line. In Symbol mode, this pin acts as TXD1_4.
Transmit Clock. TXCLK1 is sourced by the LXT973 in both 10 Mbps
and 100 Mbps modes.
2.5 MHz for 10 Mbps operation
25 MHz for 100 Mbps operation.
Receive Data.The LXT973 drives received data on these outputs,
synchronous to RXCLK1.
Receive Data Valid. The LXT973 asserts this signal when it drives
valid data on RXD0n. This output is synchronous to RXCLK1.
Receive Error. The LXT973 asserts this output when it receives
invalid symbols from the network. RXER1 is synchronous to RXCLK1.
In Symbol mode, this pin acts as RXD1_4.
Receive Clock. RXCLK1 is sourced by the LXT973 in both 10 Mbps
and 100 Mbps modes.
2.5 MHz for 10 Mbps operation
25 MHz for 100 Mbps operation.
Signal Description
Signal Description
17