SLXT973QCA3V 856775 Intel, SLXT973QCA3V 856775 Datasheet - Page 61

SLXT973QCA3V 856775

Manufacturer Part Number
SLXT973QCA3V 856775
Description
Manufacturer
Intel
Datasheet

Specifications of SLXT973QCA3V 856775

Lead Free Status / RoHS Status
Not Compliant
12.0
Datasheet
Document #: 249426
Revision #: 002
Rev. Date: March 1, 2002
Table 15. Common Register Set
Table 16. Register Bit Descriptions
Register Definitions
The LXT973 register set includes 16 registers per port. Refer to
listing.
Base Registers 0 through 8 are defined in accordance with the “Reconciliation Sublayer and Media
Independent Interface” and “Physical Layer Link Signaling for 10/100 Mbps Auto-Negotiation”
sections of the IEEE 802.3 specification.
Additional registers are defined in accordance with the IEEE 802.3 specification for adding unique
chip functions.
Address
Bit Type
LHR
R/W
WO
RO
AC
16
18
26
27
28
29
30
31
0
1
2
3
4
5
6
7
8
Control Register
Status Register
PHY Identification Register 1
PHY Identification Register 2
Auto-Negotiation Advertisement Register
Auto-Negotiation Link Partner Base Page Ability Register Refer to
Auto-Negotiation Expansion Register
Auto-Negotiation Next Page Transmit Register
Auto-Negotiation Link Partner Received Next Page
Register
Port Configuration Register
Reserved
Reserved
Special Function Register
Reserved
Reserved
Reserved
Reserved
Read and Write capable
Read Only
Write Only
Auto Clear on Read
Latched from external pins on reset
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
Register Name
Description
Table 15
Refer to
Refer to
Refer to
Refer to
Refer to
Refer to
Refer to
Refer to
Refer to
Refer to
for a complete register
Table 17 on page 62
Table 18 on page 63
Table 19 on page 64
Table 20 on page 64
Table 21 on page 65
Table 22 on page 66
Table 23 on page 67
Table 24 on page 67
Table 25 on page 68
Table 26 on page 68
Table 27 on page 70
Bit Definitions
61

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