SLXT973QC.A2 Intel, SLXT973QC.A2 Datasheet - Page 16

• Manufacturer Part Number: SLXT973QC.A2
• Manufacturer: Intel

Specifications of SLXT973QC.A2

• Lead Free Status / RoHS Status: Not Compliant

LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
2.0
16
Table 2.
Signal Descriptions
LXT973 Port 0 Signal Descriptions
44
43
42
39
38
36
37
29
30
31
32
33
35
34
45
46
Pin #
1. AI = Analog Input, AO = Analog Output, I = Input, O = Output, OD = Open Drain output,
ST = Schmitt Triggered input, TS = Tri-State-able output, SL = Slew-rate Limited output,
IP = Weak Internal Pull-up, ID = Weak Internal Pull-down.
Signal Names
TXD0_3
TXD0_2
TXD0_1
TXD0_0
TXEN0
TXER0
TXCLK0
RXD0_3
RXD0_2
RXD0_1
RXD0_0
RXDV0
RXER0
RXCLK0
COL0
CRS0
Type
O, TS
O, TS
O, TS
O, TS
O, TS
O, TS
O, TS
I
I
I
1
Transmit Data. TXD0_n is a bundle of parallel data signals driven by the
MAC controller, which TXD0<3:0> transition synchronously with respect
to the TXCLK0. TXD0<0> is the least significant bit. TXD0<3:0> are
monitored in normal mode only.
Transmit Enable. The MAC asserts TXEN0 when it drives data on
TXD0n. This signal must be synchronized to TXCLK0.
Transmit Error. TXER0 is a 100 Mbps only signal. The MAC asserts this
input when an error has occurred in the transmit data stream. When
operating at 100 Mbps, the LXT973 responds by sending "H symbols” on
the line. In Symbol mode, this pin acts as TXD0_4.
Transmit Clock. TXCLK0 is sourced by the LXT973 in both 10 Mbps
and 100 Mbps modes.
2.5 MHz for 10 Mbps operation
25 MHz for 100 Mbps operation.
Receive Data.The LXT973 drives received data on these outputs,
synchronous to RXCLK0.
Receive Data Valid. The LXT973 asserts this signal when it drives valid
data on RXD0n. This output is synchronous to RXCLK0.
Receive Error. The LXT973 asserts this output when it receives invalid
symbols from the network. RXER0 is synchronous to RXCLK0. In
Symbol mode, this pin acts as RXD0_4.
Receive Clock. RXCLK0 is sourced by the LXT973 in both 10 Mbps and
100 Mbps modes.
2.5 MHz for 10 Mbps operation
25 MHz for 100 Mbps operation.
Collision Detected. The LXT973 asserts this output when a collision is
detected. This output remains High for the duration of the collision. COL0
is asynchronous and is inactive during full-duplex operation.
Carrier Sense. During half-duplex operation, the LXT973 asserts this
output when either the transmit or receive medium is non-idle. During
full-duplex operation, CRS0 is asserted only when receive medium is
non-idle.
Signal Description
Rev. Date: March 1, 2002
Document #: 249426
Revision #: 002
Datasheet