SLXT973QC.A2 Intel, SLXT973QC.A2 Datasheet - Page 69

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SLXT973QC.A2

Manufacturer Part Number
SLXT973QC.A2
Description
Manufacturer
Intel
Datasheet

Specifications of SLXT973QC.A2

Lead Free Status / RoHS Status
Not Compliant
Datasheet
Document #: 249426
Revision #: 002
Rev. Date: March 1, 2002
Table 26. Port Configuration Register (Address 16) (Continued)
1. Refer to
2. Register bit 16.0 is latched in from hardware pins on hardware reset.
16.12
16.11
16.10
16.9
16.8
16.7
16.6
16.5
16.4
16.3
16.2
16.1
16.0
Bit
Bypass Scramble
(100BASE-TX)
Bypass 4B/5B
(100BASE-TX)
Jabber
(10BASE-T)
SQE
(10BASE-T)
TP Loopback
(10BASE-T)
CRS Select
(10BASE-T)
Reserved
PRE_EN
Reserved
10M Serial
Far End Fault
Transmission Enable
Alternate NP Feature
Fiber Select
Table 16 on page 61
Name
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
for Register Bit Descriptions.
1 = Bypass Scrambler and De-scrambler
0 = Normal operation
1 = Bypass 4B/5B encoder and decoder
0 = Normal Operation
1 = Disable Jabber
0 = Normal operation
1 = Enable Heart Beat
0 = Disable Heart Beat
1 = Disable twisted-pair loopback during half-
duplex operation
0 = Normal Operation - loopback in 10BASE-T,
half-duplex
1 = CRS de-assert extends to RXDV de-assert
0 = Normal operation
Write as 0, ignore on read
Preamble Enable.
0 = Set RXDV High coincident with SFD
1 = Set RXDV High and RXD = preamble when
CRS is asserted.
Write as 0, ignore on read
1 = 10BASE_T serial mode. 10 Mbps data is
driven serially on RXD<0> in this mode.
0 = Utilize normal MII mode-nibble.
1 = Enable Far End Fault transmission.
0 = Disable Far End Fault transmission.
1 = Enable Alternate auto-negotiation Next
Page feature.
0 = Disable Alternate auto-negotiation Next
Page feature.
1 = Select fiber mode for this port.
0 = Select twisted-pair mode for this port.
Description
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
Default
Note 2
LHR
0
0
0
0
0
1
0
0
0
0
1
0
69

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