SLXT973QC.A2 Intel, SLXT973QC.A2 Datasheet - Page 84

• Manufacturer Part Number: SLXT973QC.A2
• Manufacturer: Intel

Specifications of SLXT973QC.A2

• Lead Free Status / RoHS Status: Not Compliant

LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
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Figure 35. Fast Link Pulse Timing
Figure 36. FLP Burst Timing
Table 48. Fast Link Pulse Timing Parameters
NOTE: Twisted-pair output default pins are as follows: DPAP/N_0 and DPBP/N_1.
Clock/Data pulse width
Clock pulse to Data pulse
Clock pulse to Clock pulse
FLP burst width
FLP burst to FLP burst
Clock/Data pulses per burst
Twisted-Pair
1. Typical values are at 25°C, and are for design aid only, are not guaranteed, and are not subject to
NOTE: Twisted-pair output default pins are as follows: DPAP/N_0 and DPBP/N_1.
Twisted-Pair
production testing.
Output
Output
Parameter
Clock Pulse
FLP Burst
t4
t1
Sym
t1
t2
t3
t4
t5
–
t2
55.5
Min
115
111
17
–
8
t5
Data Pulse
Typ
116
126
2.0
63
10
t1
t3
–
1
Max
69.5
139
118
24
33
–
FLP Burst
Units
ms
ms
ns
ea
Clock Pulse
s
s
Rev. Date: March 1, 2002
Document #: 249426
Test Conditions
Revision #: 002
Datasheet
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