SLXT973QC.A2 Intel, SLXT973QC.A2 Datasheet - Page 86

• Manufacturer Part Number: SLXT973QC.A2
• Manufacturer: Intel

Specifications of SLXT973QC.A2

• Lead Free Status / RoHS Status: Not Compliant

LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
86
Figure 39. Power-Up Timing
Table 50. Power-Up Timing Parameters
Figure 40. RESET Pulse Width and Recovery Timing
Table 51. RESET Pulse Width and Recovery Timing Parameters
Voltage threshold
Power-up delay
RESET pulse width
RESET recovery delay
1. Typical values are at 25
2. Power-up delay is specified as a maximum value because it refers to the PHY’s guaranteed performance. -
1. Typical values are at 25
2. Reset recovery delay is specified as a maximum value because it refers to the PHY’s guaranteed
MDIO,etc.
the PHY comes out of reset after a delay of No MORE Than 300 S. System designers should consider
this as a minimum value. After threshold
before accessing the MDIO port.
performance. - the PHY comes out of reset after a delay of No MORE Than 300 S. System designers
should consider this as a minimum value. After de-asserting RESET, the MAC should delay No LESS than
300 S before accessing the MDIO port.
MDIO,etc.
Parameter
VCC
RESET
Parameter
2
2
Sym
v1
t1
o
o
C and are for design aid only; not guaranteed and not subject to producing testing.
C and are for design aid only; not guaranteed and not subject to producing testing.
Sym
t1
t2
Min
2.9
–
Min
10
–
V
1 is reached, the MAC should delay No LESS than 300 S
v
Typ
–
–
1
Typ
–
–
1
Max
300
–
Max
300
t
1
–
t
Units
Units
V
s
s
s
t
2
Rev. Date: March 1, 2002
Document #: 249426
Test Conditions
Test Conditions
Revision #: 002
Datasheet
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