DJLXT972ALC.A4 Cortina Systems Inc, DJLXT972ALC.A4 Datasheet
DJLXT972ALC.A4
Specifications of DJLXT972ALC.A4
Related parts for DJLXT972ALC.A4
DJLXT972ALC.A4 Summary of contents
Page 1
... The LXT972A PHY supports full-duplex operation at 10 Mbps and 100 Mbps. Operating conditions for the LXT972A PHY can be set using auto-negotiation, parallel detection, or manual control. The LXT972A PHY is fabricated with an advanced CMOS process and requires only a single 2.5/3.3 V power supply with 2.5 V MII interface support. ...
Page 2
... Cortina Systems logo are the trademarks or registered trademarks of Cortina Systems, Inc. and its subsidiaries in the U.S. and other countries. Other names and brands may be claimed as the property of others. Copyright © 2001−2007 Cortina Systems, Inc. All rights reserved. ® Cortina Systems LXT972A Single-Port 10/100 Mbps PHY Transceiver Legal Disclaimers ® PRODUCTS. Page 2 ...
Page 3
... Mbps Operation ............................................................................................................. 42 5.8.1 10BASE-T Preamble Handling .............................................................................. 42 5.8.2 10BASE-T Carrier Sense....................................................................................... 42 5.8.3 10BASE-T Dribble Bits .......................................................................................... 42 5.8.4 10BASE-T Link Integrity Test ................................................................................ 42 5.8.5 Link Failure ............................................................................................................ 43 5.8.6 10BASE-T SQE (Heartbeat) .................................................................................. 43 5.8.7 10BASE-T Jabber .................................................................................................. 43 ® Cortina Systems LXT972A Single-Port 10/100 Mbps PHY Transceiver Contents Page 3 ...
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... Magnetics Information ........................................................................................................ 47 6.2 Typical Twisted-Pair Interface ............................................................................................ 47 7.0 Electrical Specifications ............................................................................................................. 51 7.1 DC Electrical Parameters ................................................................................................... 51 7.2 AC Timing Diagrams and Parameters ................................................................................ 54 8.0 Register Definitions - IEEE Base Registers .............................................................................. 63 9.0 Register Definitions - Product-Specific Registers ................................................................... 71 10.0 Package Specifications............................................................................................................... 79 ® Cortina Systems LXT972A Single-Port 10/100 Mbps PHY Transceiver Contents Page 4 ...
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... Fast Link Pulse Timing .................................................................................................................. 59 29 MDIO Input Timing ........................................................................................................................ 60 30 MDIO Output Timing...................................................................................................................... 60 31 Power-Up Timing ........................................................................................................................... 61 32 RESET_L Pulse Width and Recovery Timing ............................................................................... 61 33 PHY Identifier Bit Mapping ...........................................................................................................66 34 LQFP Package Specifications ....................................................................................................... 79 ® Cortina Systems LXT972A Single-Port 10/100 Mbps PHY Transceiver Figures Page 5 ...
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... Register Set for IEEE Base Registers ........................................................................................... 63 39 Control Register - Address 0, Hex 0 ..............................................................................................64 40 MII Status Register #1 - Address 1, Hex 1 .................................................................................... 65 41 PHY Identification Register 1 - Address 2, Hex 2 .......................................................................... 66 42 PHY Identification Register 2 - Address 3, Hex 3 .......................................................................... 66 43 Auto-Negotiation Advertisement Register - Address 4, Hex 4....................................................... 67 44 Auto-Negotiation Link Partner Base Page Ability Register - Address 5, Hex 5 ............................. 68 45 Auto-Negotiation Expansion - Address 6, Hex 6 ...
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... Interrupt Enable Register - Address 18, Hex 12 ............................................................................ 74 52 Status Change Register - Address 19, Hex 13.............................................................................. 74 53 LED Configuration Register - Address 20, Hex 14 ........................................................................ 76 54 Digital Configuration Register - Address 26, Hex 1A..................................................................... 77 55 Transmit Control Register - Address 30, Hex 1E .......................................................................... 78 ® Cortina Systems LXT972A Single-Port 10/100 Mbps PHY Transceiver Tables Page 7 ...
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... Modified Table 29 “10BASE-T Receive Timing Modified Table 38 “register bit Map” (added Address 26 information). ® Cortina Systems LXT972A Single-Port 10/100 Mbps PHY Transceiver Revision 5.2 Revision Date: 13 September 2007 Revision 5.1 Revision Date: 23 July 2007 back into Datasheet. Revision 5.0 Revision Date: 2 July 2007 ...
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... Clock Requirements: Modified language under Clock Requirements heading. I/O Characteristics REFCLK (table): Changed values for Input Clock Duty Cycle under Min from and under Max from 60 to 65. Initial Release. ® Cortina Systems LXT972A Single-Port 10/100 Mbps PHY Transceiver Revision 003 Revision Date: 06 August 2002 26)”. 30)”. Revision 002 ...
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... Cortina Systems LXT971A, LXT972A, LXT972M Single-Port 10/ 100 Mbps PHY Specification Update ® Cortina Systems LXT971A, LXT972A, and LXT972M 3.3 V PHY Design and Layout Guide - Application Note Magnetic Manufacturers for Networking Product Applications - Application Note ® Cortina Systems LXT972A Single-Port 10/100 Mbps PHY Transceiver Document Title 1 ...
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... LED1/CFG1 Collision COL Detect RX_CLK RXD[3:0] Serial-to- Parallel RXDV Converter Carrier Sense CRS Data Valid Error Detect RX_ER ® Cortina Systems LXT972A Single-Port 10/100 Mbps PHY Transceiver Clock Generator + Manchester 10 TP OSP Encoder ™ Driver Pulse - Scrambler 100 Shaper & Encoder ...
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... Output OD Open Drain Figure 2 64-Pin LQFP Package: Pin Assignments REFCLK/XI XO MDDIS RESET_L TXSLEW0 TXSLEW1 GND VCCIO NC NC GND ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ® Cortina Systems LXT972A Single-Port 10/100 Mbps PHY Transceiver Definition 3.0 Ball and Pin Assignments RXD0 48 RXD1 47 RXD2 ...
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... VCCA 23 TPIP 24 TPIN 25 GND 26 GND 27 28 TDO 29 TMS 30 TCK 31 TRST_L 32 GND 33 PAUSE 34 GND 35 GND 36 LED/CFG3 37 LED/CFG2 ® Cortina Systems LXT972A Single-Port 10/100 Mbps PHY Transceiver Type – – NC – NC – – I – – – – AI – – – – – TDI ...
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... RXD1 48 RXD0 49 RX_DV 50 GND 51 VCCD 52 RX_CLK 53 RX_ER 54 TX_ER 55 TX_CLK 56 TX_EN 57 TXD0 58 TXD1 59 TXD2 60 TXD3 61 GND 62 COL 63 CRS 64 MDINT_L ® Cortina Systems LXT972A Single-Port 10/100 Mbps PHY Transceiver Type I/O I – – I – – – – 3.0 Ball and Pin Assignments Page 14 ...
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... Table 9, LXT972A: Configuration and LED Driver Signal Descriptions, on page 18 • Table 10, LXT972A: Power, Ground, No-Connect Signal Descriptions, on page 19 • Table 11, LXT972A: JTAG Test Signal Descriptions, on page 19 • Table 12, LXT972A: Pin Types and Modes, on page 20 ® Cortina Systems LXT972A Single-Port 10/100 Mbps PHY Transceiver Definition 4.0 Signal Descriptions Page 15 ...
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... Transmit Enable. I The MAC asserts this signal when it drives valid data on TXD. This signal must be synchronized to TX_CLK. Transmit Clock. TX_CLK is sourced by the PHY in both 10 and 100 Mbps operations. O 2.5 MHz for 10 Mbps operation 25 MHz for 100 Mbps operation. Receive Data. RXD is a group of parallel signals that transition synchronously with O respect to RX_CLK ...
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... I Clock for the MDIO serial data channel. Maximum frequency is 8 MHz. Management Data Input/Output. I/O Bidirectional serial data channel for PHY/STA communication. Management Data Interrupt. When register bit 18 Low output on this active-low pin indicates a OD status change. Interrupt is cleared by reading Register 19. ...
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... Reset. This active Low input is ORed with the control register Reset bit (register I bit 0.15). The PHY reset cycle is extended to 258 μs (nominal) after reset is de-asserted. Reference Current Bias. AI This pin provides bias current for the internal circuitry. Must be tied to ground through a 22.1 kΩ ...
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... TDI 28 TDO 29 TMS 30 TCK 31 TRST_L ® Cortina Systems LXT972A Single-Port 10/100 Mbps PHY Transceiver Type Signal Description Digital Power. – Requires a 3.3 V power supply. – Ground. MII Power. Requires either a 3 2.5 V supply. Must be supplied from the – same source used to power the MAC on the other side of the MII. ...
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... HWReset DL SFTPWRDN DL HWPWRDN HZ HZ with HZ with ISOLATE ID • Driven High (Logic 1) • Driven Low (Logic 0) • High Impedance • Internal Pull-Down (Weak) ® Cortina Systems LXT972A Single-Port 10/100 Mbps PHY Transceiver Tx/Rx RX_ER COL CLKS Output Output Output Output Active DL DL ...
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... Section 5.10, Boundary Scan (JTAG 1149.1) Functions, on page 45 5.1 Device Overview The LXT972A PHY is a single-port Fast Ethernet 10/100 PHY that supports 10 Mbps and 100 Mbps networks. It complies with applicable requirements of IEEE 802.3. It directly drives either a 100BASE-TX line or a 10BASE-T line. ...
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... Only a transformer, RJ-45 connector, load resistor and bypass capacitors are required to complete this interface. On the transmit side, the LXT972A PHY has an active internal termination and does not require external termination resistors. Cortina’s waveshaping technology shapes the outgoing signal to help reduce the need for external EMI filters. ...
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... Section 5.2.3.1.1, MDIO Addressing • Section 5.2.3.1.2, MDIO Frame Structure The LXT972A PHY supports the IEEE 802.3 MII Management Interface also known as the Management Data Input/Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the state of the LXT972A PHY. The MDIO interface consists of a physical connection, a specific protocol that runs across the connection, and an internal set of addressable registers ...
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... Connect pin ADDR0 low to get PHY address 0. • Connect pin ADDR0 high to get PHY address 1. 5.2.3.1.2 MDIO Frame Structure The physical interface consists of a data line (MDIO) and clock line (MDC). The frame structure is shown in MDIO Interface timing is given in Figure 3 ...
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... LXT972A PHY Datasheet 249186, Revision 5.2 13 September 2007 indicates a status change on the LXT972A PHY. Interrupts may be caused by any of the following four conditions: — Auto-negotiation complete — Speed status change — Duplex status change — Link status change • Register 19 provides the interrupt status. ...
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... Section 5.4.3, Reset • Section 5.4.4, Hardware Configuration Settings When the LXT972A PHY is first powered on, reset, or encounters a link failure state, it checks the MDIO register configuration bits to determine the line speed and operating conditions to use for the network link. Table 13 shows the LXT972A PHY initialization sequence. The configuration bits may be set by the Hardware Control or MDIO interface ...
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... Therefore, any changes to pin values made since the last hardware reset are not detected during a software reset. • During a software reset, registers are available for reading. To see when the LXT972A PHY has completed reset, the reset bit can be polled (that is, register bit 0.15 = 0). ® Cortina Systems LXT972A Single-Port 10/100 Mbps PHY Transceiver 5 ...
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... Establishing Link Figure 6 shows an overview of link establishment for the LXT972A PHY. Note: When a link is established by using parallel detection, the LXT972A PHY sets the duplex mode to half-duplex, as defined by the IEEE 802.3 standard. ® Cortina Systems LXT972A Single-Port 10/100 Mbps PHY Transceiver Section 5 ...
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... Manual Next Page Exchange “Next Page Exchange” information is additional information that exceeds the information required by Base Page exchange and that is sent by “Next Pages”. The LXT972A PHY fully supports the IEEE 802.3 standard method of negotiation through the Next Page exchange. ...
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... The LXT972A PHY implements the Media Independent Interface (MII) as defined by the IEEE 802.3 standard. Separate channels are provided for transmitting data from the MAC to the LXT972A PHY (TXD), and for passing data received from the line (RXD) to the MAC. Each channel has its own clock, data bus, and control signals. ...
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... MII Clocks The LXT972A PHY is the master clock source for data transmission, and it supplies both MII clocks (RX_CLK and TX_CLK). It automatically sets the clock speeds to match link conditions. • When the link is operating at 100 Mbps, the clocks are set to 25 MHz. ...
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... TX_EN after the last nibble of the packet. 5.6.3 Receive Data Valid The LXT972A PHY asserts RX_DV when it receives a valid packet. Timing changes depend on line operating speed: • For 100BASE-TX links, RX_DV is asserted from the first nibble of preamble to the last nibble of the data packet. ...
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... Error Signals When the LXT972A PHY is in 100 Mbps mode and receives an invalid symbol from the network, it asserts RX_ER and drives “0101” on the RXD pins. When the MAC asserts TX_ER, the LXT972A PHY drives “H” symbols out on the TPFOP/ N pins ...
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... Register 16 5.6.7.2 Internal Digital Loopback (Test Loopback) A test loopback function is provided for diagnostic testing of the LXT972A PHY. During test loopback, twisted-pair interfaces are disabled. Data transmitted by the MAC is internally looped back by the LXT972A PHY and returned to the MAC. Test loopback is available for both 100BASE-TX and 10BASE-T operation, and is enabled by setting the following register bits: • ...
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... During 100BASE-X operation, the LXT972A PHY transmits and receives 5-bit symbols across the network link. Figure 11 shows the structure of a standard frame packet in 100BASE-X mode. When the MAC is not actively transmitting data, the LXT972A PHY sends out Idle symbols on the line. As Figure 11 shows, the MAC starts each transmission with a preamble pattern ...
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... Figure 13 100BASE-TX Reception with No Errors RX_CLK RX_DV RXD<3:0> preamble SFD SFD DA RX_ER As shown in Figure 14, when the LXT972A PHY receives invalid symbols from the line, it asserts RX_ER. ® Cortina Systems LXT972A Single-Port 10/100 Mbps PHY Transceiver 5.7 100 Mbps Operation Scramble 4B/5B ...
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... TXD<3:0> P CRS COL Upon detection of a collision, the COL output is asserted and remains asserted for the duration of the collision as shown in Figure 16 100BASE-TX Transmission with Collision TX_CLK TX_EN TXD<3:0> P CRS COL ® Cortina Systems LXT972A Single-Port 10/100 Mbps PHY Transceiver Figure 16. ...
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... PMA Sublayer PMD Sublayer 5.7.3.1 Physical Coding Sublayer The Physical Coding Sublayer (PCS) provides the MII interface, as well as the 4B/5B encoding/decoding function. For 100BASE-TX operation, the PCS layer provides IDLE symbols to the PMD-layer line driver as long as TX_EN is de-asserted. 5.7.3.1.1 Preamble Handling When the MAC asserts TX_EN, the PCS substitutes a /J/K symbol pair, also known as the Start-of-Stream Delimiter (SSD), for the first two nibbles received across the MII ...
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... The /J/ and /K/ (SSD) code groups are always sent in pairs, and /K/ follows /J/. 3. The /T/ and /R/ (ESD) code groups are always sent in pairs, and /R/ follows /T /H/ (Error) code group is used to signal an error condition. ® Cortina Systems LXT972A Single-Port 10/100 Mbps PHY Transceiver 5B Code Name Interpretation ...
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... Link Failure Override The LXT972A PHY normally transmits data packets only if it detects the link is up. Setting register bit 16. overrides this function, allowing the LXT972A PHY to transmit data packets even when the link is down. This feature is provided as a transmit diagnostic tool. ...
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... CRS de-assertion is not aligned with TX_EN de-assertion on transmit loopbacks in half-duplex mode. 5.7.3.2.4 Receive Data Valid The LXT972A PHY asserts RX_DV to indicate that the received data maps to valid symbols. In 100 Mbps operation, RX_DV is active with the first nibble of preamble. 5.7.3.3 Twisted-Pair Physical Medium Dependent Sublayer ...
Page 42
... Dribble Bits The LXT972A PHY handles dribble bits in all modes. If one to four dribble bits are received, the nibble is passed across the MII, padded with ones if necessary. If five to seven dribble bits are received, the second nibble is not sent to the MII bus. ...
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... By default, the Signal Quality Error (SQE) or heartbeat function is disabled on the LXT972A PHY. To enable this function, set register bit 16 When this function is enabled, the LXT972A PHY asserts its COL output for bit times (BT) after each packet. For SQE timing parameters, see on page 58 ...
Page 44
... September 2007 5.9.2 Monitoring Next Page Exchange The LXT972A PHY offers an Alternate Next Page mode to simplify the next page exchange process. Normally, register bit 6.1 (Page Received) remains set until read. When Alternate Next Page mode is enabled, register bit 6.1 is automatically cleared whenever a new negotiation process takes place ...
Page 45
... Note: The direct drive LED outputs in this diagram are shown as active Low. 5.10 Boundary Scan (JTAG 1149.1) Functions The LXT972A PHY includes a IEEE 1149.1 boundary scan test port for board level testing. All digital input, output, and input/output pins are accessible. Note: For the related BSDL file, contact your local sales office or access the Cortina website (www ...
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... Update 4 System Function 5.10.5 Device ID Register Table 17 lists the bits for the Device ID register. For the current version of the JEDEC continuation characters, see the specification update for the LXT972A PHY. Table 17 Device ID Register Bits 31:28 Bits 27:12 Version Part ID (Hex) XXXX 03CB 1 ...
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... Application Information 6.1 Magnetics Information The LXT972A PHY requires a 1:1 ratio for both the receive and transmit transformers. The transformer isolation voltage should be rated protect the circuitry from static voltages across the connectors and cables. For transformer/magnetics requirements, see Table 18 ...
Page 48
... V current source. A separate ferrite bead (rated at 50 mA) should be used to supply center tap current. 2. The 100 Ω transmit load termination resistor typically required is integrated in the PHY. 3. Magnetics without a receive pair center-tap do not require termination. 4. RJ-45 connections shown are for a standard switch application. ...
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... V current source. A separate ferrite bead (rated at 50 mA) should be used to supply center-tap current. 2. The 100 Ω transmit load termination resistor typically required is integrated in the PHY. 3. Magnetics without a receive pair center tap do not require termination. 4. RJ-45 connections shown for standard NIC. TX/RX crossover may be required for repeater and switch applications. ® ...
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... LXT972A PHY Datasheet 249186, Revision 5.2 13 September 2007 Figure 21 show a typical media independent interface (MII) for the LXT972A PHY. Figure 21 Typical Media Independent Interface MAC ® Cortina Systems LXT972A Single-Port 10/100 Mbps PHY Transceiver TX_EN TX_ER TXD[3:0] TX_CLK RX_CLK Trans- LXT97x ...
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... Revision 5.2 13 September 2007 7.0 Electrical Specifications This chapter includes test specifications for the LXT972A PHY. These specifications are guaranteed by test except where noted “by design”. Caution: Exceeding the absolute maximum rating values may cause permanent damage. Functional operation under these conditions is not implied. ...
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... MII digital I/O pins are tolerant inputs. 2. Typical values are at 25 °C and are for design aid only, not guaranteed, and not subject to production testing. 3. Parameter is guaranteed by design and not subject to production testing. ® Cortina Systems LXT972A Single-Port 10/100 Mbps PHY Transceiver Sym I CC Icc I ...
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... Typical values are at 25 °C and are for design aid only, not guaranteed, and not subject to production testing. 2. Measured at the line side of the transformer, line replaced by 100 Ω (+/-1%) resistor. ® Cortina Systems LXT972A Single-Port 10/100 Mbps PHY Transceiver 1 Symbol Min Typ ...
Page 54
... AC Timing Diagrams and Parameters See the following timing diagrams and AC parameters: • Figure 22, 100BASE-TX Receive Timing, on page 55 • Figure 23, 100BASE-TX Transmit Timing, on page 56 • Figure 24, 10BASE-T Transmit Timing, on page 57 ® Cortina Systems LXT972A Single-Port 10/100 Mbps PHY Transceiver Symbol Min Typ Max Transmitter V 2 ...
Page 55
... Figure 32, RESET_L Pulse Width and Recovery Timing, on page 61 Figure 22 100BASE-TX Receive Timing 0 ns TPI CRS RX_DV RXD[3:0] RX_CLK COL Note: Timing diagram depicts 4B mode. ® Cortina Systems LXT972A Single-Port 10/100 Mbps PHY Transceiver 7.2 AC Timing Diagrams and 250 B3492-03 Parameters Page 55 ...
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... BT (Bit Time) is the duration of one bit as transferred to and from the Mac and is the reciprocal of the bit rate. 100BASE-T bit time = 10 3. RX_ER is not shown in the figure. Figure 23 100BASE-TX Transmit Timing TXCLK TX_EN TXD[3:0] TPO CRS Note: Timing diagram depicts 4B mode. ® Cortina Systems LXT972A Single-Port 10/100 Mbps PHY Transceiver 1 Sym Min Typ 3 setup – – ...
Page 57
... BT (Bit Time) is the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit rate. 10BASE-T bit time = 10 Figure 24 10BASE-T Transmit Timing TX_CLK t TXD, TX_EN, TX_ER CRS TPO ® Cortina Systems LXT972A Single-Port 10/100 Mbps PHY Transceiver 1 Sym Min Typ t1 10 – – t3 4.2 – ...
Page 58
... Parameter COL (SQE) Delay after TX_EN off COL (SQE) Pulse duration 1. Typical values are at 25 °C and are for design aid only, not guaranteed, and not subject to production testing. ® Cortina Systems LXT972A Single-Port 10/100 Mbps PHY Transceiver Symbol Min Typ ...
Page 59
... FLP burst width FLP burst to FLP burst Clock/Data pulses per burst 1. Typical values are at 25 °C and are for design aid only, not guaranteed, and not subject to production testing. ® Cortina Systems LXT972A Single-Port 10/100 Mbps PHY Transceiver Clock Pulse Data Pulse ...
Page 60
... STA MDC to MDIO output delay, sourced by PHY MDC period 1. Typical values are at 25° C and are for design aid only, not guaranteed, and not subject to production testing. ® Cortina Systems LXT972A Single-Port 10/100 Mbps PHY Transceiver 7.2 AC Timing Diagrams and Symbol ...
Page 61
... Power-up delay is specified as a maximum value because it refers to the PHY guaranteed performance. The PHY comes out of reset after a delay of no more than 300 μ s. System designers should consider this value as a minimum value. After threshold v1 is reached, the MAC should delay no less than 300 μ s before accessing the MDIO port ...
Page 62
... Reset Recovery Delay is specified as a maximum value because it refers to the PHY guaranteed performance. The PHY comes out of reset after a delay of no more than 300 μ s. System designers should consider this value as a minimum value. After de-asserting RESET_L, the MAC should delay no less than 300 μ ...
Page 63
... September 2007 8.0 Register Definitions - IEEE Base Registers This chapter includes definitions for the IEEE base registers used by the LXT972A PHY. Section 9.0, Register Definitions - Product-Specific Registers additional product-specific LXT972A PHY registers, which are defined in accordance with the IEEE 802.3 standard for adding unique device functions. ...
Page 64
... Mbps (not supported Reserved 0 = Disable auto-negotiation process 1 = Enable auto-negotiation process 0 = Normal operation 1 = Power-down 0 = Normal operation 1 = Electrically isolate PHY from MII 0 = Normal operation 1 = Restart auto-negotiation process 0 = Half-duplex 1 = Full-duplex 0 = Disable COL signal test 1 = Enable COL signal test 0.6 0.13 Speed Selected 0 ...
Page 65
... PHY able to perform half-duplex 100BASE PHY not able to operate at 10 Mbps full-duplex mode 1 = PHY able to operate at 10 Mbps in full-duplex mode 0 = PHY not able to operate at 10 Mbps in half- duplex 1 = PHY able to operate at 10 Mbps in half-duplex mode 0 = PHY not able to perform full-duplex 100BASE-T2 ...
Page 66
... Note: The Intel OUI is 00207B hex ® Cortina Systems LXT972A Single-Port 10/100 Mbps PHY Transceiver Description The PHY identifier is composed of bits 3 through 18 of the Organizationally Unique Identifier (OUI). Description The PHY identifier is composed of bits 19 through 24 of the OUI. 6 bits containing manufacturer’s part number. ...
Page 67
... Pause operation disabled Pause operation enabled for full-duplex link 100BASE-T4 capability is not available 100BASE-T4 capability is available. Note: The LXT972A PHY does not support 100BASE-T4 but allows this bit to be set to advertise in the auto-negotiation sequence for 100BASE-T4 operation. An external 100BASE-T4 PHY can be switched in if this capability is desired ...
Page 68
... Selector Field 5.4:0 S<4:0> Read Only ® Cortina Systems LXT972A Single-Port 10/100 Mbps PHY Transceiver 8.0 Register Definitions - IEEE Description 0 = Link Partner has no ability to send multiple pages Link Partner has ability to send multiple pages Link Partner has not received Link Code Word from the LXT972A PHY ...
Page 69
... Unformatted Code Field Read Only. R/W = Read/Write ® Cortina Systems LXT972A Single-Port 10/100 Mbps PHY Transceiver 8.0 Register Definitions - IEEE Description Ignore when read. This bit indicates the status of the auto-negotiation variable base page. It flags synchronization with the auto-negotiation state diagram, allowing detection of interrupted links ...
Page 70
... Unformatted Code Field Read Only. ® Cortina Systems LXT972A Single-Port 10/100 Mbps PHY Transceiver 8.0 Register Definitions - IEEE Description 0 = Link Partner has no additional next pages to send 1 = Link Partner has additional next pages to send 0 = Link Partner has not received Link Code Word from LXT972A PHY ...
Page 71
... Register Definitions - Product-Specific Registers This chapter includes definitions of product-specific LXT972A PHY registers that are defined in accordance with the IEEE 802.3 standard for adding unique device functions. (For definitions of the IEEE base registers used by the LXT972A PHY, see Register Definitions - IEEE Base • ...
Page 72
... Description Always LXT972A PHY is not operating 100BASE-TX mode LXT972A PHY is operating in 100BASE-TX mode LXT972A PHY is not transmitting a packet LXT972A PHY is transmitting a packet LXT972A PHY is not receiving a packet LXT972A PHY is receiving a packet collision Collision is occurring Link is down Link is up Half-duplex Full-duplex LXT972A PHY is in manual mode. ...
Page 73
... Always Polarity is not reversed Polarity is reversed. Note: Polarity is not a valid status in 100 Mbps mode The LXT972A PHY is not Pause capable The LXT972A PHY is Pause capable error occurred 1 = Error occurred (Remote Fault, jabber, parallel detect fault) Note: The register bit is cleared when the registers that generate the error condition are read ...
Page 74
... SPEEDCHG 19.5 DUPLEXCHG 1. R/W = Read/Write Read Only Self Clearing. ® Cortina Systems LXT972A Single-Port 10/100 Mbps PHY Transceiver Description Write as ‘0’. Ignore on Read. Write as ‘0’. Ignore on Read. Mask for Auto Negotiate Complete not allow event to cause interrupt Enable event to cause interrupt. ...
Page 75
... Reserved 19.0 Reserved 1. R/W = Read/Write Read Only Self Clearing. ® Cortina Systems LXT972A Single-Port 10/100 Mbps PHY Transceiver Description Link Status Change Status Link Change has not occurred since last reading this register Link Change has occurred since last reading this register. ...
Page 76
... Collision status is the secondary LED driver. The LED changes state (blinks) when a collision occurs. 5. Values are approximations. Not guaranteed or production tested. ® Cortina Systems LXT972A Single-Port 10/100 Mbps PHY Transceiver Description 0000 =Display Speed Status (Continuous, Default) 0001 =Display Transmit Status (Stretched) ...
Page 77
... Show Symbol Error 26.8:6 Reserved 1. R/W = Read /Write Read Only ® Cortina Systems LXT972A Single-Port 10/100 Mbps PHY Transceiver Description 0000 =Display Speed Status 0001 =Display Transmit Status 0010 =Display Receive Status (Default) 0011 = Display Collision Status 0100 =Display Link Status ...
Page 78
... Values are approximations and may vary outside indicated values based upon implementation loading conditions. 2. R/W = Read/Write 3. Latch State during Reset is based on the state of hardware configuration pins at RESET_L. ® Cortina Systems LXT972A Single-Port 10/100 Mbps PHY Transceiver Description Write as ‘0’. Ignore on Read. Write as ‘0’. Ignore on Read. Write as ‘0’. Ignore on Read. Description Write as ‘ ...
Page 79
... Max A – 1.60 A 0.05 0. 1.35 1. 0.17 0.27 D 11.85 12.15 D 9.9 10 11.85 12.15 E 9.9 10 0.50 BSC L 0.45 0.75 L 1.00 REF 1 θ θ Basic Spacing between Centers ® Cortina Systems LXT972A Single-Port 10/100 Mbps PHY Transceiver 10.0 Package Specifications θ θ θ 3 Page 79 ...
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For additional product and ordering information: www.cortina-systems.com ~ End of Document ~ TM ...