1892YLF IDT, Integrated Device Technology Inc, 1892YLF Datasheet

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1892YLF

Manufacturer Part Number
1892YLF
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of 1892YLF

Lead Free Status / RoHS Status
Compliant
10Base-T/100Base-TX Integrated PHYceiver
General
The ICS1892, an enhanced version of the ICS 1890, is a
fully integrated, physical-layer device (PHY) that is
compliant with both the 10Base-T and 100Base-TX
CSMA/CD Ethernet Standard, ISO/IEC 8802-3.
The ICS1892 incorporates digital signal processing (DSP)
in its Physical Medium Dependent (PMD) sublayer. As a
result, it can transmit and receive data on unshielded
twisted-pair (UTP) category 5 cable with attenuation in
excess of 24 dB at 100 MHz. With this ICS-patented
technology, the ICS1892 can virtually eliminate errors from
killer packets.
The ICS1892 supports a broad range of applications: data
terminal equipm ent (netwo rk in terf ace card s and
motherboards), switches, repeaters, bridges, and routers. Its
Media Independent Interface (MII) supports direct
c h i p - t o - c h i p a n d m o t h e r b o a r d - t o - d a u g h t e r b o ar d
connections as well as connections to an MII connector and
cable. The ICS1892 also provides a Serial Management
Interface for exchanging command and status information
with a Station Management (STA) entity.
The ICS1892 Media Dependent Interface (MDI) can be
configured to provide either half- or full-duplex operation at
data rates of 10 MHz or 100 MHz. The MDI configuration
can be done manually (with input pins or control register
settings) or automatically (using the Auto-Negotiation
features). When the ICS1892 Auto-Negotiation sublayer is
enabled, it exchanges technology capability data with its
remote link partner and automatically selects the
highest-performance operating mode they have in common.
1892 Rev. D, 2/26/01
ICS1892 Block Diagram
MAC/Repeater
Management
10/100 MII or
MII Serial
Alternate
Interface
Interface
Extended
Interface
Register
Integrated Circuit Systems, Inc.
MUX
Set
MII
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any information
being relied upon by the customer is current and accurate.
PCS
Synthesizer
Low-Jitter
Frame
CRS/COL
Detection
Parallel to Serial
4B/5B
Clock
ICS1892
Clock
PMA
100Base-T
10Base-T
Power
Clock Recovery
Link Monitor
Signal Detection
Error Detection
Features
NOTE: EOL for non-green parts to occur on
5/13/10 per PDN U-09-01
Supports category 5 cables with attenuation in excess of
24 dB at 100 MHz across a temperature range from -5° to
+85° C
DSP-based baseline wander correction to virtually
eliminate killer packets across temperature range of from
-5° to +85° C
Low-power, 0.5-micron CMOS
Single 5.0-V power supply.
Single-chip, fully integrated PHY provides PCS, PMA,
PMD, and AUTONEG sublayers of IEEE standard
10Base-T and 100Base-TX IEEE 802.3 compliant
Fully integrated, DSP-based PMD includes:
Highly configurable design supports:
MAC/Repeater Interface can be configured as:
Provides Loopback Modes for Diagnostic Functions
Small Footprint 64-pin Low-Profile LQFP and MQFP
packages available
– Adaptive equalization and baseline wander correction
– Transmit wave shaping and stream cipher scrambler
– MLT-3 encoder and NRZ/NRZI encoder
– Node, repeater, and switch applications
– Managed and unmanaged applications
– 10M or 100M half- and full-duplex modes
– Parallel detection
– Auto-negotiation, with Next Page capabilities
– 10M or 100M Media Independent Interface
– 100M Symbol Interface (bypasses the PCS)
– 10M 7-wire Serial Interface
TP_PMD
Configuration
and Status
LEDs and PHY
Address
MLT-3
Stream Cipher
Adaptive Equalizer
Baseline Wander
Correction
Document Type:
Document Stage: Released
Negotiation
Integrated
Switch
Auto-
Data Sheet
Modules and
Interface to
Connector
Magnetics
Twisted-
RJ45
Pair

Related parts for 1892YLF

1892YLF Summary of contents

Page 1

... CSMA/CD Ethernet Standard, ISO/IEC 8802-3. The ICS1892 incorporates digital signal processing (DSP) in its Physical Medium Dependent (PMD) sublayer result, it can transmit and receive data on unshielded twisted-pair (UTP) category 5 cable with attenuation in excess 100 MHz. With this ICS-patented technology, the ICS1892 can virtually eliminate errors from killer packets ...

Page 2

ICS1892 Data Sheet Section Chapter 1 Abbreviations and Acronyms................................................................9 Chapter 2 Conventions and Nomenclature..........................................................11 Chapter 3 ICS 1892 Enhanced Features.............................................................. 13 Chapter 4 Overview of the ICS 1892 .................................................................... 15 4.1 100Base-TX Operation .............................................................................. 16 4.2 10Base-T Operation .................................................................................. 16 ...

Page 3

ICS1892 Section 7.3 Functional Block: 100Base-X PCS and PMA Sublayers ........................... 41 7.3.1 PCS Sublayer ............................................................................................ 41 7.3.2 PMA Sublayer ............................................................................................ 41 7.3.3 PCS/PMA Transmit Modules ..................................................................... 42 7.3.4 PCS/PMA Receive Modules ...................................................................... 43 7.3.5 PCS Control Signal Generation ................................................................. ...

Page 4

... Auto-Negotiation Ability (bit 1.3) ................................................................ 69 8.3.11 Link Status (bit 1.2) .................................................................................... 69 8.3.12 Jabber Detect (bit 1.1) ............................................................................... 70 8.3.13 Extended Capability (bit 1.0) ..................................................................... 70 8.4 Register 2: PHY Identifier Register ............................................................ 71 ICS1892, Rev. D, 2/26/01 © 2000-2001, Integrated Circuit Systems, Inc. All rights reserved. Table of Contents Title 4 Table of Contents ...

Page 5

... ICS1892 Section 8.5 Register 3: PHY Identifier Register ............................................................ 73 8.5.1 OUI bits 19-24 (bits 3.15:10) ..................................................................... 73 8.5.2 Manufacturer's Model Number (bits 3.9:4) ................................................ 73 8.5.3 Revision Number (bits 3.3:0) ..................................................................... 74 8.6 Register 4: Auto-Negotiation Register ....................................................... 75 8.6.1 Next Page (bit 4.15) ................................................................................... 75 8.6.2 IEEE Reserved Bit (bit 4.14) ...................................................................... 76 8.6.3 Remote Fault (bit 4.13) .............................................................................. 76 8 ...

Page 6

... Register 16: Extended Control Register .................................................... 86 8.11.1 Command Override Write Enable (bit 16.15) ............................................ 87 8.11.2 ICS Reserved (bits 16.14:11) .................................................................... 87 8.11.3 PHY Address (bits 16.10:6) ....................................................................... 87 8.11.4 Stream Cipher Scrambler Test Mode (bit 16.5) ......................................... 87 8.11.5 ICS Reserved (bit 16.4) ............................................................................. 87 8.11.6 NRZ/NRZI Encoding (bit 16.3) ................................................................... 87 8.11.7 Invalid Error Code Test (bit 16 ...

Page 7

... Pin Listings by Alphabetical Pin Name .................................................... 103 9.2 ICS 1892 Pin Descriptions ....................................................................... 104 9.2.1 Transformer Interface Pins ...................................................................... 104 9.2.2 Multifunction (Multiplexed) Pins: PHY Address and LED Pins ................ 105 9.2.3 Configuration Pins ................................................................................... 106 9.2.4 MAC/Repeater Interface Pins .................................................................. 109 9.2.5 Reserved Pins ......................................................................................... 118 9 ...

Page 8

... Jabber Timing ........................................................................ 142 10.5.20 10Base-T: Normal Link Pulse Timing ...................................................... 143 10.5.21 Auto-Negotiation Fast Link Pulse Timing ................................................ 144 Chapter 11 Physical Dimensions of ICS 1892 Package................................... 145 Chapter 12 Ordering Information ....................................................................... 147 ICS1892, Rev. D, 2/26/01 © 2000-2001, Integrated Circuit Systems, Inc. All rights reserved. ...

Page 9

ICS1892 Chapter 1 Abbreviations and Acronyms Table 1-1 lists and interprets the abbreviations and acronyms used throughout this data sheet. Table 1-1. Abbreviations and Acronyms Abbreviation / Acronym 4B/5B 4-Bit / 5-Bit Encoding/Decoding ANSI American National Standards Institute CMOS complimentary ...

Page 10

... Abbreviation / Acronym OUI Organizationally Unique Identifier PCS Physical Coding sublayer PHY physical-layer device The ICS1892 is a physical-layer device, also referred ‘PHY’ or ‘PHYceiver’. (The ICS 1890 is also a physical-layer device.) PLL phase-locked loop PMA Physical Medium Attachment PMD Physical Medium Dependent ...

Page 11

ICS1892 Chapter 2 Conventions and Nomenclature Table 2-1 lists and explains the conventions and nomenclature used throughout this data sheet. Table 2-1. Conventions and Nomenclature Item Asterisk (*) Bits Code groups Colon (:) Numbers Pin (or signal) names ICS1892, Rev. ...

Page 12

ICS1892 Data Sheet Table 2-1. Conventions and Nomenclature (Continued) Item Registers Signal references Symbols Terms: ‘set’, ‘active’, ‘asserted’, Terms: ‘cleared’, ‘de-asserted’, ‘inactive’ Terms: ‘twisted-pair receiver’ Terms: ‘twisted-pair transmitter’ ICS1892, Rev. D, 2/26/01 © 2000-2001, Integrated Circuit Systems, Inc. All rights ...

Page 13

... The ICS1892 employs an advanced digital signal processing (DSP) architecture that improves the 100Base-TX Receiver performance beyond that of any other PHY in the market. Specifically: a. The ICS1892 DSP-based, adaptive equalization process allows the ICS1892 to accommodate a maximum cable attenuation/insertion loss of 29 dB, which is nearly equivalent to the attenuation loss of a 150-meter Category 5 cable ...

Page 14

ICS1892 Data Sheet Table 3-1. Summary of Differences between ICS 1890 and ICS1892 Registers Register. ICS 1890 Bit(s) Function 1.6 Reserved 3.9:4 Model Number 3:0 Revision Number 6.2 Next Page Able 7.15:0 Not applicable (N/A) 8.15:0 N/A 9.15:0 IEEE reserved. ...

Page 15

... ICS1892 converts and decodes a serial bit stream (acquired from an isolation transformer that interfaces with the medium) into sequential nibbles. It subsequently presents these nibbles to its MAC/Repeater Interface. The ICS1892 implements the OSI model’s physical layer, consisting of the following, as defined by the ISO/IEC 8802-3 standard: • ...

Page 16

... For 100M data transmission, the ICS1892 MAC/Repeater Interface can be configured to provide either a 100M Media Independent Interface (MII 100M Symbol Interface. With the Symbol Interface configuration, the data stream bypasses the ICS1892 Physical Coding sublayer (PCS) and the following results: 1. The ICS1892 shifts the responsibility of performing the 4B/5B translation to the MAC/repeater result, the requirement is for a 5-bit data path between the MAC/repeater and the ICS1892 ...

Page 17

ICS1892 Chapter 5 Operating Modes Overview The ICS1892 operating modes and interfaces are configurable with one of two methods. The first configuration method is by using hardware pins. With this method, the HW/SW (hardware/software) pin determines whether it is the ...

Page 18

... Latches the Serial Management Port Address of the ICS1892 into the Extended Control Register, bits 16.10:6. [See Section 8.11.3, “PHY Address (bits 3. Enables all its internal modules and state machines 4. Sets all Management Register bits to either (1) their default values or (2) the values specified by their associated ICS1892 input pins, as determined by the HW/SW pin 5 ...

Page 19

ICS1892 5.1.2 Specific Reset Operations This section discusses the following specific ways that the ICS1892 can be reset: • Hardware reset (using the RESET* pin) • Power-on reset (applying power to the ICS1892) • Software reset (using Control Register bit ...

Page 20

... Address into the Extended Control Register. [For information on the Serial Management Port Address, see Section 8.11.3, “PHY Address (bits 3. The Control Register bit 0.15 does not represent the status of a hardware reset self-clearing bit that is used to initiate a software reset. During a hardware or power-on reset, Control Register bit 0.15 does not get set to logic one ...

Page 21

ICS1892 5.3 Automatic Power-Saving Operations The ICS1892 has power-saving features that automatically minimize its total power consumption while it is operating. Table 5-1 lists the ICS1892 automatic power-saving features for the various modes. Table 5-1. Automatic Power-Saving Features, 10Base-T and ...

Page 22

... Operations The ICS1892 10Base-T mode is another primary operating mode that provides 10Base-T physical layer (PHY) services as defined in the ISO/IEC 8802-3 standard. In the 10Base-T mode, the ICS1892 is a 10M translator between a MAC/repeater and the physical transmission medium. As such, the ICS1892 has two interfaces, both of which are fully configurable: one to the MAC/repeater and one to the Link Segment ...

Page 23

... ICS1892 Chapter 6 Interface Overviews The ICS1892 MAC/Repeater Interface is fully configurable, thereby allowing it to accommodate many different applications. This chapter includes overviews of the following MAC/repeater-to-PHY interfaces: • Section 6.1, “MII Data Interface” • Section 6.2, “100M Symbol Interface” • Section 6.3, “10M Serial Interface” ...

Page 24

... Through an MII connector and cable (in a manner similar to AUI connections) Clause 22 of the ISO/IEC standard defines the MII between an Ethernet PHY and the MAC/Reconciliation sublayer for 10-Mbps and 100-Mbps operations. The specification supports a variety of physical media, including 100Base-TX, 100Base-T4, and 100Base-FX. The specification is such that use of a specific medium for the Link Segment is transparent to the MAC ...

Page 25

ICS1892 6.2 100M Symbol Interface The 100M Symbol Interface has a primary objective of supporting 100Base-TX repeater applications for which the repeater requires only recovered parallel data and for which the repeater provides all the necessary framing and control functions. ...

Page 26

... MDIO RXCLK SRCLK RXD0 SRD0 RXD1 SRD1 RXD2 SRD2 RXD3 SRD3 RXDV No connect. (Data exchanged between the MAC/repeater and a PHY is not framed in the 100M Symbol Interface mode. Therefore, RXDV has no meaning.) RXER SRD4 TXCLK STCLK TXD0 STD0 TXD1 STD1 TXD2 STD2 ...

Page 27

ICS1892 6.3 10M Serial Interface When the Mac/Repeater Interface is configured as a 10M Serial Interface, the ICS1892 and the MAC/repeater exchange a framed, serial bit stream along with associated control signals. The 10M Serial Interface configuration is ideally suited ...

Page 28

ICS1892 Data Sheet Table 6-2 lists the pin mappings for the ICS1892 10M Serial Interface mode. Table 6-2. Pin Mappings for 10M Serial Interface Mode Default 10M / 100M MII Pin Names COL 10COL CRS 10CRS LSTA LSTA MDC MDC ...

Page 29

ICS1892 6.4 Link Pulse Interface The Link Pulse Interface allows an application to control each step in the auto-negotiation process except for the actual generation and reception of 10Base-T link pulses (that is, Normal Link Pulses). The ICS1892 MAC/Repeater Interface ...

Page 30

... The ISO/IEC 8802-3 standard specifies a two-wire Serial Management Interface and protocol as part of the MII. This interface is used to exchange configuration, control, and status information between a Station Management entity (an STA) and a physical layer device (a PHY). The ISO/IEC standard specifies a frame structure and protocol for this interface as well as a set of Management Registers that it can access. The ICS1892 implementation of this interface complies fully with the ISO/IEC standard ...

Page 31

ICS1892 6.7.2 Clock Source: Crystal Figure 6-1 shows the recommended configuration when a crystal is used to supply the ICS1892 clock source. As shown, connect the two leads of the crystal between the ICS1892 pins REF_IN and REF_OUT. To properly ...

Page 32

... The ICS1892 multiplexes each of these five LED output signals with one of the five PHY address inputs. The following example shows how this multiplexing takes place: 1. The PHY Address bit P0 and the link activity LED (AC) share pin 58. During a reset of the ICS1892, the signal on the link activity LED pin (as well as the other four LED pins) become inputs. ...

Page 33

ICS1892 Chapter 7 Functional Blocks This chapter discusses the following ICS1892 functional blocks. • Section 7.1, “Functional Block: Media Independent Interface” • Section 7.2, “Functional Block: Auto-Negotiation” • Section 7.3, “Functional Block: 100Base-X PCS and PMA Sublayers” • Section 7.4, ...

Page 34

... ICS1892 MIIs can support two data transfer rates: 25 MHz (for 100Base-TX operations) and 2.5 MHz (for 10Base-T operations). The Media Independent Interface (MII) consists of two primary components interface between a MAC (Media Access Control sublayer) and the PHY (that is, the ICS1892). This MAC-PHY part of the MII consists of three subcomponents synchronous Transmit interface that includes the following signals: ...

Page 35

ICS1892 7.2 Functional Block: Auto-Negotiation The auto-negotiation logic of the ICS1892 has the following main functions: • To determine the capabilities of the remote link partner, (that is, the device at the other end of the link segment’s medium or ...

Page 36

... ICS1892 Data Sheet 7.2.1 Auto-Negotiation General Process The Auto-Negotiation sublayer uses a physical signaling technique that is transparent at the packet level and all higher protocol levels. This technique builds on the link pulse mechanism employed in 10Base-T operations and is fully compliant with clause 28 of the ISO/IEC 8802-3 standard. ...

Page 37

ICS1892 7.2.2 Auto-Negotiation: Parallel Detection The ICS1892 supports parallel detection therefore compatible with networks that do not support the auto-negotiation process. When enabled, the Auto-Negotiation sublayer can detect legacy 10Base-T link partners as well as 100Base-TX link partners ...

Page 38

ICS1892 Data Sheet 7.2.4 Auto-Negotiation: Reset and Restart If enabled, execution of the ICS1892 auto-negotiation process occurs at power-up and upon management request. There are two primary ways to begin the Auto-Negotiation state machine: • ICS1892 reset • Auto-Negotiation Restart ...

Page 39

ICS1892 7.2.5 Auto-Negotiation: Progress Monitor Under typical circumstances, the Auto-Negotiation sublayer can establish a connection with the ICS1892’s remote link partner. However, some situations can prevent the auto-negotiation process from properly achieving this goal. For these situations, the ICS1892 has ...

Page 40

ICS1892 Data Sheet For example, if the status bits have a value of 3h and the auto-negotiation process moves into: • State 1, the Auto-Negotiation Progress Monitor does not update the status bits to indicate the new state. • State ...

Page 41

... Receive modules are inactive. However, its PCS control functions (CRS and COL) remain operational. 7.3.2 PMA Sublayer The ICS1892 100Base-X PMA Sublayer consists of two interfaces: one to the Physical Coding sublayer and the other to the Physical Medium Dependent sublayer. Functionally, the PMA sublayer is responsible for the following: • Link Monitoring • ...

Page 42

... PMA Transmit Module The ICS1892 PMA Transmit module accepts a serial bit stream from the PCS and converts it into NRZI format. Subsequently, the PMA passes the NRZI bit stream to the Twisted-Pair Physical Medium Dependent (TP-PMD) sublayer. The ICS1892 PMA Transmit module uses a digital PLL to synthesize a transmit clock from the Clock Reference Interface. When the ICS1892 is configured for an interface that is: • ...

Page 43

ICS1892 7.3.4 PCS/PMA Receive Modules Both the PCS and PMA sublayers have Receive modules. 7.3.4.1 PCS Receive Module The ICS1892 PCS Receive module accepts both a serial bit stream and a clock signal from the PMA sublayer. The PCS Receive ...

Page 44

... NRZI Decoding – The Receive module performs the NRZI decoding on the serial bit stream received from the Twisted-Pair Physical Medium Dependent (TP-PMD) sublayer. It converts the bit stream to a unipolar, positive, binary format which the PMA subsequently passes it to the PCS. – The PMA extracts the clock embedded in the serial data stream. ...

Page 45

ICS1892 7.3.6 4B/5B Encoding/Decoding The 4B/5B coding methodology maps each 4-bit nibble to a 5-bit symbol (also called a “code group”). There are 32 five-bit symbols, which include the following: • Of the 32 five-bit symbols, 16 five-bit symbols are ...

Page 46

... Functional Block: 100Base-TX TP-PMD Operations The ICS1892 supports both 10Base-T and 100Base-TX operations. The ICS1892 TP-PMD modules perform 100Base-TX Twisted-Pair Physical Media Dependent (TP-PMD) stream cipher scrambling/descrambling and MLT-3 encoding/decoding (3-level, multi-level transition) in compliance with the ANSI Standard X3.263: 199X FDDI TP-PMD as called out in the ISO/IEC 8802-3 standard. The ICS1892 TP-PMD also performs DC restoration and adaptive equalization on the received signals ...

Page 47

ICS1892 7.4.4 100Base-TX Operation: Adaptive Equalizer The ICS1892 TP-PMD sublayer employs adaptive equalization circuitry to compensate for signal amplitude and phase distortion incurred from the transmission medium data rate of 100 Mbps, the transmission medium (that is, the ...

Page 48

... Typically, for each magnetic module there are two isolation transformers: one for the ICS1892 Twisted-Pair Transmitter and the other for the ICS1892 Twisted-Pair Receiver. For both 10Base-T and 100Base-TX operations, these isolation transformers provide both physical isolation as well as the means for coupling a signal between the ICS1892 and the medium. ...

Page 49

ICS1892 7.5 Functional Block: 10Base-T Operations The ICS1892 supports both 10Base-T and 100Base-TX operations. When configured for 10Base-T mode, the MAC/Repeater Interface can provide either a 10M MII (Media Independent Interface 10M Serial Interface. The Twisted-Pair Interface is ...

Page 50

ICS1892 Data Sheet 7.5.4 10Base-T Operation: Idle The ICS1892 10Base-T Idle Function transmits link pulses in the absence of data (that is, when the MAC/repeater is not requiring it to transmit any data). During this time the link is Idle, ...

Page 51

... For example, in 10Base-T mode, the ICS1892 appends an IDL to the end of each packet during data transmission. The receiving PHY sees this IDL and removes it from the data stream. Enabling this function requires the receiving PHY to confirm the presence of this IDL before declaring a link valid. • ...

Page 52

ICS1892 Data Sheet 7.5.9 10Base-T Operation: Jabber According to the ISO/IEC 8802-3 standard, a jabber function detects abnormally long transmissions and takes appropriate actions to avoid them. The ICS1892 Jabber Function monitors the data stream sent to the Twisted-Pair Transmitter ...

Page 53

ICS1892 7.5.11 10Base-T Operation: Twisted-Pair Transmitter For both 10Base-T and 100Base-TX operations, the ICS1892 uses the same Twisted-Pair Transmit pins (TP_TXP and TP_TXN) as well as the same internal functional module. The twisted-pair transmitter module is a current-driven, differential driver ...

Page 54

... Typically, for each magnetic module there are two isolation transformers: one for the ICS1892 Twisted-Pair Transmitter and the other for the ICS1892 Twisted-Pair Receiver. For both 10Base-T and 100Base-TX operations, these isolation transformers provide both physical isolation as well as the means for coupling a signal between the ICS1892 and the medium. ...

Page 55

... Management Frame Structure The Management Interface is a bi-directional serial interface to exchange configuration, control, and status data between a PHY such as the ICS1892 and the STA. The PHY and STA exchange data by using the defined register set. The STA initiates all transactions. ...

Page 56

... Management Frame PHY Address The ISO/IEC specification is such that a maximum of 32 PHYs can use one set of MDC and MDIO interface pins. An STA uniquely identifies each of the PHYs sharing a management interface by using the 5-bit PHY Address field, PHYAD. A valid Management Frame includes a PHYAD field. ...

Page 57

ICS1892 7.6.2.6 Management Frame Turnaround A valid Management Frame includes a turnaround field (TA), which is a 2-bit time space between the REGAD field and the Data field. This field requires two bit times and allows the ICS1892 and the ...

Page 58

... Section 8.3, “Register 1: Status Register” • Section 8.4, “Register 2: PHY Identifier Register” • Section 8.5, “Register 3: PHY Identifier Register” • Section 8.6, “Register 4: Auto-Negotiation Register” • Section 8.7, “Register 5: Auto-Negotiation Link Partner Ability Register” • ...

Page 59

... Management Register Set Outline This section outlines the ICS1892 Management Register set. Management Register Set that the ICS1892 implements. Table 8-1. ISO/IEC-Specified Management Register Set Register Address 0 Control 1 Status 2,3 PHY Identifier 4 Auto-Negotiation Advertisement 5 Auto-Negotiation Link Partner Ability 6 Auto-Negotiation Expansion 7 Auto-Negotiation Next Page Transmit 8 ...

Page 60

... For some bits, the default value depends on the state of a particular pin at reset (that is, the state value of a pin is latched at reset.) An example of pins that have a default condition that depends on the state of the pin at reset are the PHY / LED pins (P0AC, P1CL, P2LI, P3TD, and P4RD) discussed in Interface” ...

Page 61

ICS1892 8.1.4 Management Register Bit Special Functions The three types of special functions for the Management Register bits include the following: 8.1.4.1 Latching High Bits The purpose of a latching high (LH) bit is to record an event ...

Page 62

... IEEE reserved 0.1 IEEE reserved 0.0 IEEE reserved † Whenever the PHY address of • Is equal to 00000 (binary), the Isolate bit 0.10 is logic one. • Is not equal to 00000, the Isolate bit 0.10 is logic zero. ‡ As per the IEEE Std 802.3u, during any write operation to any bit in this register, the STA must write the default value to all Reserved bits ...

Page 63

ICS1892 8.2.2 Loopback Enable (bit 0.14) This bit controls the Loopback mode for the ICS1892. Setting this bit to logic: • Zero disables the Loopback mode. • One enables the Loopback mode by disabling the Twisted-Pair Transmitter, the Twisted-Pair Receiver, ...

Page 64

... Management Interface continues to operate normally (that is, bit 0.10 does not affect the Management Interface). The default value for bit 0.10 depends upon the PHY address of • Is equal to 00000b, then the default value of bit 0.10 is logic one, and the ICS1892 isolates itself from the MAC/Repeater Interface. • ...

Page 65

ICS1892 8.2.8 Duplex Mode (bit 0.8) This bit provides a means of controlling the ICS1892 Duplex Mode. Its operation depends on several other functions, including the HW/SW input pin and the Auto-Negotiation Enable bit (bit 0.12). When the ICS1892 is ...

Page 66

... No remote Fault Detected Remote fault detected N/A Always 1: PHY has Auto-Negotiation ability Link is invalid/down Link is valid/established No jabber condition Jabber condition detected N/A Always 1: PHY has extended capabilities 66 Chapter 8 Management Register Set Acronyms”. Ac- SF De- Hex cess fault RO – ...

Page 67

ICS1892 8.3.2 100Base-TX Full Duplex (bit 1.14) The STA reads this bit to learn if the ICS1892 can support 100Base-TX, Full Duplex operations. The ISO/IEC specification requires that the ICS1892 must set bit 1.14 to logic: • Zero if it ...

Page 68

ICS1892 Data Sheet 8.3.6 IEEE Reserved Bits (bits 1.10:7) The IEEE reserves these bits for future use. When an STA: • Reads a reserved bit, the ICS1892 returns a logic zero. • Writes a reserved bit, the STA must use ...

Page 69

ICS1892 8.3.9 Remote Fault (bit 1.4) The STA reads bit 1.4 to determine if a Remote Fault exists. The ICS1892 sets bit 1.4 based on the Remote Fault bit received from its remote link partner. The ICS1892 receives the Remote ...

Page 70

ICS1892 Data Sheet 8.3.12 Jabber Detect (bit 1.1) The purpose of this bit is to allow an STA to read this bit to determine if the ICS1892 detects a Jabber condition. The ISO/IEC specification defines the requirements for detection of ...

Page 71

... Manufacturer’s PHY Revision Number, discussed in All of the bits in the two PHY Identifier Registers are Command Override Write bits. An STA can read them at any time without condition. However, an STA can modify these register bits only when the Command Register Override bit (bit 16.15) is enabled with a logic one. ...

Page 72

ICS1892 Data Sheet IEEE-Assigned Organizationally Unique Identifier (OUI) For each manufacturing organization, the IEEE assigns an 3-octet OUI. For Integrated Circuit Systems, Inc. the IEEE-assigned 3-octet OUI is 00A0BEh. The binary representation of an OUI is formed by expressing each ...

Page 73

... Manufacturer’s PHY Revision Number All of the bits in the two PHY Identifier Registers are Command Override Write bits. An STA can read them at any time without condition. However, An STA can modify these register bits only when the Command Register Override bit (bit 16.15) is enabled with a logic one. ...

Page 74

ICS1892 Data Sheet 8.5.3 Revision Number (bits 3.3:0) Table 8-10 lists the valid ICS1892 revision numbers, which are 4-bit binary numbers stored in bits 3.3:0. Table 8-10. ICS1892 Revision Number Decimal Bits 3.3:0 0 0000 ICS1892, Rev. D, 2/26/01 © ...

Page 75

... ICS1892 advertises (that is, exchanges) capability data with its remote link partner by using a pre-defined Link Code Word. The Link Code Word is embedded in the Fast Link Pulses exchanged between PHYs, when the ICS1892 has its Auto-Negotiation sublayer enabled. The value of the Link Control Word is established based on the value of the bits in this register ...

Page 76

ICS1892 Data Sheet 8.6.2 IEEE Reserved Bit (bit 4.14) The ISO/IEC specification reserves this bit for future use. However, the ISO/IEC Standard also defines bit 4.14 as the Acknowledge bit. When this reserved bit is read by an STA, the ...

Page 77

ICS1892 8.6.4.1 Technology Ability Field: Hardware Mode When the ICS1892 is operating in Hardware mode (that is, the HW/SW pin is logic zero), these TAF bits are Read Only bits. The default value of these bits depends on the signal ...

Page 78

ICS1892 Data Sheet 8.7 Register 5: Auto-Negotiation Link Partner Ability Register Table 8-12 lists the bits for the Auto-Negotiation Link Partner Ability Register. An STA uses this register to determine the capabilities being advertised by the remote link partner. During ...

Page 79

ICS1892 8.7.2 Acknowledge (bit 5.14) The ISO/IEC specification defines bit 5.14 as the Acknowledge bit. When this bit is a: • Zero, it indicates that the remote link partner has not received the ICS1892 Link Control Word. • One, it ...

Page 80

ICS1892 Data Sheet 8.8 Register 6: Auto-Negotiation Expansion Register Table 8-13 lists the bits for the Auto-Negotiation Expansion Register, which indicates the status of the Auto-Negotiation process. Note: For an explanation of acronyms used in Table 8-13. Auto-Negotiation Expansion Register ...

Page 81

ICS1892 8.8.2 Parallel Detection Fault (bit 6.4) The ICS1892 sets this bit to a logic one if a parallel detection fault is encountered. A parallel detection fault occurs when the ICS1892 cannot disseminate the technology being used by its remote ...

Page 82

ICS1892 Data Sheet 8.9 Register 7: Auto-Negotiation Next Page Transmit Register Table 8-14 lists the bits for the Auto-Negotiation Next Page Transmit Register, which establishes the contents of the Next Page Link Control Word that is transmitted during Next Page ...

Page 83

... ICS1892 8.9.1 Next Page (bit 7.15) This bit is used by a PHY/STA to enable the transmission of Next Pages following the base Link Control Word as long as the remote link partner supports the Next Page features of Auto-Negotiation. This bit is used to establish the state of the Next Page (NP) bit of the Next Page Link Control Word (that is, the NP bit of the Next Page Link Control Word tracks this bit) ...

Page 84

ICS1892 Data Sheet 8.10 Register 8: Auto-Negotiation Next Page Link Partner Ability Register Table 8-15 lists the bits for the Auto-Negotiation Next Page Link Partner Ability Register, which establishes the contents of the Next Page Link Control Word that is ...

Page 85

... ICS1892 8.10.1 Next Page (bit 8.15) This bit is used by a PHY/STA to enable the transmission of Next Pages following the base Link Control Word as long as the remote link partner supports the Next Page features of Auto-Negotiation. This bit is used to establish the state of the Next Page (NP) bit of the Next Page Link Control Word (that is, the NP bit of the Next Page Link Control word tracks this bit) ...

Page 86

... ICS reserved 16.10 PHY Address Bit 4 16.9 PHY Address Bit 3 16.8 PHY Address Bit 2 16.7 PHY Address Bit 1 16.6 PHY Address Bit 0 16.5 Stream Cipher Test Mode Normal operation 16.4 ICS reserved 16.3 NRZ/NRZI encoding 16.2 Transmit invalid codes 16.1 ICS reserved 16 ...

Page 87

... PHY Address (bits 16.10:6) These five bits hold the Serial Management Port Address of the ICS1892. During either a hardware reset or a power-on reset, the PHY address is read from the LED interface. (For information on the LED interface, see Section 6.9, “Status Interface” ...

Page 88

ICS1892 Data Sheet 8.11.7 Invalid Error Code Test (bit 16.2) The Invalid Error Code Test bit allows an STA to force the ICS1892 to transmit symbols that are typically classified as invalid. The purpose of this test bit is to ...

Page 89

ICS1892 8.12 Register 17: Quick Poll Detailed Status Register Table 8-18 lists the bits for the Quick-Poll Detailed Status Register. This register is a 16-bit read-only register used to provide an STA with detailed status of the ICS1892 operations. During ...

Page 90

ICS1892 Data Sheet 8.12.1 Data Rate (bit 17.15) The Data Rate bit indicates the ‘selected technology’. If the ICS1892 is in: • Hardware mode, the value of this bit is determined by the 10/100SEL input pin. • Software mode, the ...

Page 91

ICS1892 8.12.3 Auto-Negotiation Progress Monitor (bits 17.13:11) The Auto-Negotiation Progress Monitor consists of the Auto-Negotiation Complete bit (bit 17.4) and the three Auto-Negotiation Monitor bits (bits 17.13:11). The Auto-Negotiation Progress Monitor continually examines the state of the Auto-Negotiation Process State ...

Page 92

ICS1892 Data Sheet 8.12.5 PLL Lock Error (bit 17.9) The Phase Locked Loop (PLL) Lock Error bit indicates to an STA whether the ICS1892 has ever experienced a PLL Lock Error. A PLL Lock Error occurs when a the PLL ...

Page 93

ICS1892 8.12.8 Halt Symbol (bit 17.6) The Halt Symbol bit indicates to an STA the detection of an Halt Symbol in a 100Base data stream by the ICS1892. During reception of a valid packet, the ICS1892 examines each symbol to ...

Page 94

ICS1892 Data Sheet 8.12.13 Remote Fault (bit 17.1) Bit 17.1 is functionally identical to bit 1.4. 8.12.14 Link Status (bit 17.0) Bit 17.0 is functionally identical to bit 1.2. ICS1892, Rev. D, 2/26/01 © 2000-2001, Integrated Circuit Systems, Inc. All ...

Page 95

ICS1892 8.13 Register 18: 10Base-T Operations Register The 10Base-T Operations Register provides an STA with the ability to monitor and control the ICS1892 activity while the ICS1892 is operating in 10Base-T mode. Note: 1. For an explanation of acronyms used ...

Page 96

ICS1892 Data Sheet 8.13.2 Polarity Reversed (bit 18.14) The Polarity Reversed bit is used to inform an STA whether the ICS1892 has detected that the signals on the Twisted-Pair Receive Pins (TP_RXP and TP_RXN) are reversed. When the signal polarity ...

Page 97

ICS1892 8.13.8 Link Loss Inhibit (bit 18.1) The Link Loss Inhibit bit allows an STA to prevent the ICS1892 from dropping the link in 10Base-T mode. When an STA sets this bit to logic: • Zero, the state machine behaves ...

Page 98

ICS1892 Data Sheet 8.14 Register 19: Extended Control Register 2 The Extended Control Register provides more refined control of the internal ICS1892 operations. Note: 1. For an explanation of acronyms used in 2. During any write operation to any bit ...

Page 99

ICS1892 8.14.1 Node/Repeater Configuration (bit 19.15) The Node/Repeater Configuration bit directly indicates the state of the NOD/REP input pin. When this bit is logic: • Zero, the NOD/REP input pin is pulled down, which instructs the operation code to operate ...

Page 100

ICS1892 Data Sheet 8.14.5 Automatic 10Base-T Power-Down (bit 19.1) The Automatic 10Base-T Power Down bit provides an STA the means of enabling the ICS1892 to automatically shut down 10Base-T support functions when 100Base-TX operations are being employed. When this bit ...

Page 101

ICS1892 Chapter 9 Pin Diagram, Listings, and Descriptions 9.1 ICS1892 Pin Diagram NOD/REP 1 10/100SEL 2 10TCSR 3 100TCSR 4 TP_TXP 5 TP_TXN TP_RXP 10 TP_RXN ...

Page 102

ICS1892 Data Sheet 9.1.1 Pin Listing by Pin Number Table 9-1 lists the ICS1892 pins by pin number. Table 9-1. ICS1892 Pins, by Pin Number Pin Pin Name No. 1 NOD/REP 2 10/100SEL 3 10TCSR 4 100TCSR 5 TP_TXP 6 ...

Page 103

ICS1892 9.1.2 Pin Listings by Alphabetical Pin Name Table 9-2 lists the ICS1892 pins alphabetically by pin name. Table 9-2. ICS1892 Pins, by Alphabetical Pin Name Pin Name Pin Number 10/100SEL 2 10/LP 28 10TCSR 3 100TCSR 4 ANSEL 64 ...

Page 104

ICS1892 Data Sheet 9.2 ICS1892 Pin Descriptions The tables in this section list the ICS1892 pins by their functional grouping. 9.2.1 Transformer Interface Pins Table 9-3 lists the pins for the transformer interface group of pins. Table 9-3. Transformer Interface ...

Page 105

... ICS1892 9.2.2 Multi-Function (Multiplexed) Pins: PHY Address and LED Pins Table 9-4 lists the pins for the multifunction group of pins (that is, the multiplexed PHY Address / LED pins). Note: 1. During either a power-on reset or a hardware reset, each multi-function configuration pin is an input that is sampled when the ICS1892 exists the reset state ...

Page 106

ICS1892 Data Sheet 9.2.3 Configuration Pins Table 9-5 lists the configuration pins. Table 9-5. Configuration Pins Pin Pin Name Number Type 10/100SEL 2 Input or Output 10/LP 28 Input 10TCSR 3 Input 100TCSR 4 Input ANSEL 64 Input or Output ...

Page 107

ICS1892 Table 9-5. Configuration Pins (Continued) Pin Pin Name Number Type DPXSEL 24 Input or Output HW/SW 23 Input LOCK 27 Output LSTA 21 Output MII/SI 19 Input NOD/REP 1 Input ICS1892, Rev. D, 2/26/01 © 2000-2001, Integrated Circuit Systems, ...

Page 108

ICS1892 Data Sheet Table 9-5. Configuration Pins (Continued) Pin Pin Name Number Type REF_IN 53 Input REF_OUT 52 Input RESET* 22 Input ICS1892, Rev. D, 2/26/01 © 2000-2001, Integrated Circuit Systems, Inc. All rights reserved. Chapter 9 Pin Diagram, Listings, ...

Page 109

ICS1892 9.2.4 MAC/Repeater Interface Pins This section lists pin descriptions for each of the following interfaces • Section 9.2.4.1, “MAC/Repeater Interface Pins for Media Independent Interface” • Section 9.2.4.2, “MAC/Repeater Interface Pins for 100M Symbol Interface” • Section 9.2.4.3, “MAC/Repeater ...

Page 110

ICS1892 Data Sheet Table 9-6. MAC/Repeater Interface Pins: Media Independent Interface (MII) (Continued) Pin Pin Pin Name Number Type MDIO 30 Input/ Output RXCLK 37 RXD0, 35, RXD1, 34, RXD2, 33, RXD3 32 ICS1892, Rev. D, 2/26/01 © 2000-2001, Integrated ...

Page 111

... Low, the MAC indicates that it is not in a tri-state condition. • High, the MAC indicates that tri-state condition. In this case, the ICS1892 acts to ensure that only one PHY is active at a time. • PHY address 00 will also act as RXTRI. Transmit Clock. ...

Page 112

... Pin Description Transmit Enable. The signal on this pin indicates to the ICS1892 that the MAC/repeater is sending valid data nibbles for transmission on the physical media. • Synchronous with the assertion of TXEN, the ICS1892 begins reading the data nibbles on the transmit data lines and transmitting them over the media. • ...

Page 113

ICS1892 9.2.4.2 MAC/Repeater Interface Pins for 100M Symbol Interface Table 9-7 lists the MAC/Repeater Interface pin descriptions for the 100M Symbol Interface. Table 9-7. MAC/Repeater Interface Pins: 100M Symbol Interface MII Pin 100M Pin Name Symbol No. Pin Name COL ...

Page 114

... Low, the MAC indicates that it is not in a tri-state condition. • High, the MAC indicates that tri-state condition. In this case, the ICS1892 acts to ensure that only one PHY is active at a time. Symbol Transmit Clock. This pin’s description is the same as that given in ...

Page 115

ICS1892 9.2.4.3 MAC/Repeater Interface Pins for 10M Serial Interface Table 9-8 lists the MAC/Repeater Interface pin descriptions for the 10M Serial Interface. Table 9-8. MAC/Repeater Interface Pins: 10M Serial Interface MII Pin 10M Pin Name Serial No. Pin Name COL ...

Page 116

... Low, the MAC indicates that it is not in a tri-state condition. • High, the MAC indicates that tri-state condition. In this case, the ICS1892 acts to ensure that only one PHY is active at a time. No Transmit Error. connect For the 10M Serial Interface, this pin connect. For more ...

Page 117

... Low, the MAC indicates that it is not in a tri-state condition. • High, the MAC indicates that tri-state condition. In this case, the ICS1892 acts to ensure that only one PHY is active at a time. Link (Pulse Interface) Transmit Clock. This pin’s description is the same as that given in No Transmit Data 0– ...

Page 118

ICS1892 Data Sheet Table 9-9. MAC/Repeater Interface Pins: Link Pulse Interface (Continued) MII Pin Link Pin Name Pluse No. Pin Name TXEN – 44 TXER LPTX 42 9.2.5 Reserved Pins Table 9-10 lists the reserved pins. Table 9-10. Reserved Pins ...

Page 119

ICS1892 Table 9-11. Ground and Power Pins Pin Name Pin Number ICS1892, Rev. D, 2/26/01 © 2000-2001, Integrated Circuit Systems, Inc. All ...

Page 120

ICS1892 Data Sheet Chapter 10 DC and AC Operating Conditions 10.1 Absolute Maximum Ratings Table 10-1 lists the absolute maximum ratings for the ICS1892. Stresses above these ratings can cause permanent damage to the ICS1892. These ratings, which are standard ...

Page 121

ICS1892 10.3 Recommended Component Values Table 10-3 lists the recommended component values for the ICS1892. Table 10-3. Recommended Component Values Parameter Crystal Frequency 10TCSR Resistor Value 100TCSR Resistor Value LED Resistor Value Note: Do not put bypass capacitors across the ...

Page 122

ICS1892 Data Sheet 10.4 DC Operating Characteristics This section lists the DC operating characteristics for the ICS1892. 10.4.1 DC Operating Characteristics for Supply Current Table 10-4 lists the DC operating characteristics for the supply current to the ICS1892. Note: All ...

Page 123

ICS1892 10.4.4 DC Operating Characteristics for Media Independent Interface Table 10-7 lists DC operating characteristics for the Media Independent Interface (MII) for the ICS1892. Table 10-7. DC Operating Characteristics for Media Independent Interface Parameter MII Input Pin Capacitance MII Output ...

Page 124

ICS1892 Data Sheet 10.5 Timing Diagrams 10.5.1 Timing for Clock Reference In (REF_IN) Pin Table 10-8 lists the significant time periods for signals on the clock reference in (REF_IN) pin. shows the timing diagram for the time periods. Note: The ...

Page 125

ICS1892 10.5.2 Timing for Transmit Clock (TXCLK) Pin Table 10-9 lists the significant time periods for signals on the Transmit Clock (TXCLK) pin for the various interfaces. Figure 10-2 shows the timing diagram for the time periods. Table 10-9. Transmit ...

Page 126

ICS1892 Data Sheet 10.5.3 Timing for Receive Clock (RXCLK) Pin Table 10-10 lists the significant time periods for signals on the Receive Clock (RXCLK) pin for the various interfaces. Figure 10-3 shows the timing diagram for the time periods. Table ...

Page 127

ICS1892 10.5.4 100M MII / 100M Stream Interface: Synchronous Transmit Timing Table 10-11 lists the significant time periods for the 100M MII / 100M Stream Interface synchronous transmit timing (which consists of timings of signals on the TXD[3:0], TXEN, TXER, ...

Page 128

ICS1892 Data Sheet 10.5.5 10M MII: Synchronous Transmit Timing Table 10-12 lists the significant time periods for the 10M MII synchronous transmit timing (which consists of timings of signals on the TXD[3:0], TXEN, TXER, and TXCLK pins). for the time ...

Page 129

ICS1892 10.5.6 MII / 100M Stream Interface: Synchronous Receive Timing Table 10-13 lists the significant time periods for the MII / 100M Stream Interface synchronous receive timing (which consists of timings of signals on the RXD[3:0], RXDV, RXER, and RXCLK ...

Page 130

ICS1892 Data Sheet 10.5.7 MII Management Interface Timing Table 10-14 lists the significant time periods for the MII Management Interface timing (which consists of timings of signals on the MDC and MDIO pins). Table 10-14. MII Management Interface Timing Time ...

Page 131

ICS1892 10.5.8 10M Serial Interface: Receive Latency Table 10-15 lists the significant time periods for the 10M Serial Interface timing (which consists of timings of signals on the following pins: • TP_RX (the MDI mapping of the 10M/100M MII TP_RXP ...

Page 132

ICS1892 Data Sheet 10.5.9 10M Media Independent Interface: Receive Latency Table 10-16 lists the significant time periods for the 10M MII timing (which consists of timings of signals on the following pins: TP_RX (that is, the MII TP_RXP and TP_RXN ...

Page 133

ICS1892 10.5.10 10M Serial Interface: Transmit Latency Table 10-17 lists the significant time periods for the 10M Serial Interface transmit latency. The time periods consist of timings of signals on the following pins: • 10TXEN (the 10M Serial Interface mapping ...

Page 134

ICS1892 Data Sheet 10.5.11 10M Media Independent Interface: Transmit Latency Table 10-18 lists the significant time periods for the 10M MII transmit latency. The time periods consist of timings of signals on the following pins: TXEN, TXCLK, TXD (that is, ...

Page 135

ICS1892 10.5.12 MII / 100M Stream Interface: Transmit Latency Table 10-19 lists the significant time periods for the MII / 100 Stream Interface transmit latency. The time periods consist of timings of signals on the following pins: TXEN, TXCLK, TXD ...

Page 136

ICS1892 Data Sheet 10.5.13 MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission) Table 10-20 lists the significant time periods for the MII carrier assertion/de-assertion during half-duplex transmission. The time periods consist of timings of signals on the following pins: TXEN, TXCLK, and CRS. ...

Page 137

ICS1892 10.5.14 100M MII / 100M Stream Interface: Receive Latency Table 10-21 lists the significant time periods for the 100M MII / 100M Stream Interface receive latency. The time periods consist of timings of signals on the following pins: TP_RX ...

Page 138

ICS1892 Data Sheet 10.5.15 Media Dependent Interface: Input-to-Carrier Assertion/De-Assertion Table 10-22 lists the significant time periods for the MDI input-to-carrier assertion/de-assertion. The time periods consist of timings of signals on the following pins: CRS, COL, and TP_RX (that is, the ...

Page 139

ICS1892 10.5.16 Reset: Power-On Reset Table 10-23 lists the significant time periods for the power-on reset (which consists of timings of signals on the V and TXCLK pins). DD Table 10-23. Power-On Reset Timing Time Period ≥ 4. ...

Page 140

ICS1892 Data Sheet 10.5.17 Reset: Hardware Reset and Power-Down Table 10-24 lists the significant time periods for the hardware reset and power-down reset (which consists of timings of signals on the REF_IN, RESET*, and TXCLK pins). the time periods. Table ...

Page 141

ICS1892 10.5.18 10Base-T: Heartbeat Timing (SQE) Table 10-25 lists the significant time periods for the 10Base-T heartbeat (that is, the Signal Quality Error, which consists of timings of signals on the TXEN, TXCLK, and COL pins). diagram for the time ...

Page 142

ICS1892 Data Sheet 10.5.19 10Base-T: Jabber Timing Table 10-26 lists the significant time periods for the 10Base-T jabber. The time periods consist of timings of signals on the following pins: TXEN, COL, and TP_TX (that is, the TP_TXP and TP_TXN ...

Page 143

ICS1892 10.5.20 10Base-T: Normal Link Pulse Timing Table 10-27 lists the significant time periods for the 10Base-T Normal Link Pulse (which consists of timings of signals on the TP_TXP pin). Table 10-27. 10Base-T Normal Link Pulse Timing Time Parameter Period ...

Page 144

ICS1892 10.5.21 Auto-Negotiation Fast Link Pulse Timing Table 10-28 lists the significant time periods for the ICS1892 Auto-Negotiation Fast Link Pulse (which consists of timings of signals on the TP_TXP and TP_TXN pins). for the time periods. Table 10-28. Auto-Negotiation ...

Page 145

... ICS1892 Chapter 11 Physical Dimensions of ICS1892 Package This section gives the physical dimensions for the various ICS1892 packages. • The lead count (N) for all packages is 64 leads. • The nominal footprint (that is the body) for all packages is 2.0 mm. Table 11-1 lists the ICS1892 physical dimensions, which are shown in Table 11-1 ...

Page 146

... Figure 11-1. ICS1892 Physical Dimensions ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ...

Page 147

ICS1892 Chapter 12 Ordering Information NOTE: EOL for non-green parts to occur on 5/13/10 per PDN U-09-01 Figure 12-1 shows ordering information for the ICS1892 packages, which include the following: • ICS1892Y • ICS1892Y-10 • ICS1892Y-14 Figure 12-1. ICS1892 Ordering ...

Page 148

ICS1892 Data Sheet Integrated Circuit Systems, Inc. Corporate Headquarters: Silicon Valley: Web Site: ICS1892, Rev. D, 2/26/01 © 2000-2001, Integrated Circuit Systems, Inc. All rights reserved. 2435 Boulevard of the Generals P.O. Box 968 Valley Forge, PA 19482-0968 Telephone: 610-630-5300 ...

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