XC5VLX50T-1FFG665C Xilinx Inc, XC5VLX50T-1FFG665C Datasheet

FPGA, VIRTEX-5 LXT, 50K, 665FCBGA

XC5VLX50T-1FFG665C

Manufacturer Part Number
XC5VLX50T-1FFG665C
Description
FPGA, VIRTEX-5 LXT, 50K, 665FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG665C

No. Of Logic Blocks
7200
Family Type
Virtex-5
No. Of Speed Grades
1
Total Ram Bits
2211840
No. Of I/o's
360
Clock Management
DCM, PLL
I/o Supply Voltage
3.3V
Operating Frequency Max
550MHz
Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
665-BBGA, FCBGA
Core Supply Voltage Range
1V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
122-1565
DS100 (v5.0) February 6, 2009
General Description
The Virtex®-5 family provides the newest most powerful features in the FPGA market. Using the second generation ASMBL™ (Advanced
Silicon Modular Block) column-based architecture, the Virtex-5 family contains five distinct platforms (sub-families), the most choice
offered by any FPGA family. Each platform contains a different ratio of features to address the needs of a wide variety of advanced logic
designs. In addition to the most advanced, high-performance logic fabric, Virtex-5 FPGAs contain many hard-IP system level blocks,
including powerful 36-Kbit block RAM/FIFOs, second generation 25 x 18 DSP slices, SelectIO™ technology with built-in digitally-
controlled impedance, ChipSync™ source-synchronous interface blocks, system monitor functionality, enhanced clock management tiles
with integrated DCM (Digital Clock Managers) and phase-locked-loop (PLL) clock generators, and advanced configuration options.
Additional platform dependant features include power-optimized high-speed serial transceiver blocks for enhanced serial connectivity,
PCI Express® compliant integrated Endpoint blocks, tri-mode Ethernet MACs (Media Access Controllers), and high-performance
PowerPC® 440 microprocessor embedded blocks. These features allow advanced logic designers to build the highest levels of
performance and functionality into their FPGA-based systems. Built on a 65-nm state-of-the-art copper process technology, Virtex-5
FPGAs are a programmable alternative to custom ASIC technology. Most advanced system designs require the programmable strength
of FPGAs. Virtex-5 FPGAs offer the best solution for addressing the needs of high-performance logic designers, high-performance DSP
designers, and high-performance embedded systems designers with unprecedented logic, DSP, hard/soft microprocessor, and
connectivity capabilities. The Virtex-5 LXT, SXT, TXT, and FXT platforms include advanced high-speed serial connectivity and
link/transaction layer capability.
Summary of Virtex-5 FPGA Features
© 2006–2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other
countries. PowerPC is a trademark of IBM Corp. and is used under license. PCI, PCI Express, PCIe, and PCI-X are trademarks of PCI-SIG. All other trademarks are the property
of their respective owners.
DS100 (v5.0) February 6, 2009
Product Specification
Five platforms LX, LXT, SXT, TXT, and FXT
Cross-platform compatibility
Most advanced, high-performance, optimal-utilization,
FPGA fabric
Powerful clock management tile (CMT) clocking
36-Kbit block RAM/FIFOs
High-performance parallel SelectIO technology
Virtex-5 LX: High-performance general logic applications
Virtex-5 LXT: High-performance logic with advanced serial
connectivity
Virtex-5 SXT: High-performance signal processing
applications with advanced serial connectivity
Virtex-5 TXT: High-performance systems with double
density advanced serial connectivity
Virtex-5 FXT: High-performance embedded systems with
advanced serial connectivity
LXT, SXT, and FXT devices are footprint compatible in the
same package using adjustable voltage regulators
Real 6-input look-up table (LUT) technology
Dual 5-LUT option
Improved reduced-hop routing
64-bit distributed RAM option
SRL32/Dual SRL16 option
Digital Clock Manager (DCM) blocks for zero delay
buffering, frequency synthesis, and clock phase shifting
PLL blocks for input jitter filtering, zero delay buffering,
frequency synthesis, and phase-matched clock division
True dual-port RAM blocks
Enhanced optional programmable FIFO logic
Programmable
-
-
Built-in optional error-correction circuitry
Optionally program each block as two independent 18-Kbit
blocks
1.2 to 3.3V I/O Operation
Source-synchronous interfacing using ChipSync™
technology
Digitally-controlled impedance (DCI) active termination
Flexible fine-grained I/O banking
High-speed memory interface support
True dual-port widths up to x36
Simple dual-port widths up to x72
R
0
0
www.xilinx.com
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Advanced DSP48E slices
Flexible configuration options
System Monitoring capability on all devices
Integrated Endpoint blocks for PCI Express Designs
Tri-mode 10/100/1000 Mb/s Ethernet MACs
RocketIO GTP transceivers 100 Mb/s to 3.75 Gb/s
RocketIO GTX transceivers 150 Mb/s to 6.5 Gb/s
PowerPC 440 Microprocessors
65-nm copper CMOS process technology
1.0V core voltage
High signal-integrity flip-chip packaging available in standard
or Pb-free package options
25 x 18, two’s complement, multiplication
Optional adder, subtracter, and accumulator
Optional pipelining
Optional bitwise logical functionality
Dedicated cascade connections
SPI and Parallel FLASH interface
Multi-bitstream support with dedicated fallback
reconfiguration logic
Auto bus width detection capability
On-chip/Off-chip thermal monitoring
On-chip/Off-chip power supply monitoring
JTAG access to all monitored quantities
LXT, SXT, TXT, and FXT Platforms
Compliant with the PCI Express Base Specification 1.1
x1, x4, or x8 lane support per block
Works in conjunction with RocketIO™ transceivers
LXT, SXT, TXT, and FXT Platforms
RocketIO transceivers can be used as PHY or connect to
external PHY using many soft MII (Media Independent
Interface) options
LXT and SXT Platforms
TXT and FXT Platforms
FXT Platform only
RISC architecture
7-stage pipeline
32-Kbyte instruction and data caches included
Optimized processor interface structure (crossbar)
Virtex-5 Family Overview
Product Specification
1

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XC5VLX50T-1FFG665C Summary of contents

Page 1

R DS100 (v5.0) February 6, 2009 General Description The Virtex®-5 family provides the newest most powerful features in the FPGA market. Using the second generation ASMBL™ (Advanced Silicon Modular Block) column-based architecture, the Virtex-5 family contains five distinct platforms (sub-families), ...

Page 2

... XC5VLX220 160 x 108 34,560 2,280 XC5VLX330 240 x 108 51,840 3,420 XC5VLX20T 3,120 210 XC5VLX30T 4,800 320 XC5VLX50T 120 x 30 7,200 480 XC5VLX85T 120 x 54 12,960 840 XC5VLX110T 160 x 54 17,280 1,120 XC5VLX155T 160 x 76 24,320 1,640 XC5VLX220T 160 x 108 34,560 ...

Page 3

R Virtex-5 FPGA Logic • On average, one to two speed grade improvement over Virtex-4 devices • Cascadable 32-bit variable shift registers or 64-bit distributed memory capability • Superior routing architecture with enhanced diagonal routing supports block-to-block connectivity with minimal ...

Page 4

Virtex-5 Family Overview Digitally Controlled Impedance (DCI) Active I/O Termination • Optional series or parallel termination • Temperature and voltage compensation • Makes board layout much easier − Reduces resistors − Places termination in the ideal location, at the signal ...

Page 5

R RocketIO GTP Transceivers (LXT/SXT only) • Full-duplex serial transceiver capable of 100 Mb/s to 3.75 Gb/s baud rates • 8B/10B, user-defined FPGA logic encoding options • Channel bonding support • CRC generation and checking • Programmable pre-emphasis ...

Page 6

Virtex-5 Family Overview Architectural Description Virtex-5 FPGA Array Overview Virtex-5 devices are user-programmable gate arrays with various configurable elements and embedded cores optimized for high-density and high-performance system designs. Virtex-5 devices implement the following functionality: • I/O blocks provide the ...

Page 7

R Virtex-5 FPGA Features This section briefly describes the features of the Virtex-5 family of FPGAs. Input/Output Blocks (SelectIO) IOBs are programmable and can be categorized as follows: • Programmable single-ended or differential (LVDS) operation • Input block with an ...

Page 8

Virtex-5 Family Overview Global Clocking The CMTs and global-clock multiplexer buffers provide a complete solution for designing high-speed clock networks. Each CMT contains two DCMs and one PLL. The DCMs and PLLs can be used independently or extensively cascaded. Up ...

Page 9

R Virtex-5 LXT, SXT, TXT, and FXT Platform Features This section briefly describes blocks available only in LXT, SXT, TXT, and FXT devices. Tri-Mode (10/100/1000 Mb/s) Ethernet MACs Virtex-5 LXT, SXT, TXT, and FXT devices contain up to eight embedded ...

Page 10

Virtex-5 Family Overview Virtex-5 TXT and FXT Platform Features This section describes blocks only available in TXT and FXT devices. RocketIO GTX Serial Transceivers (TXT/FXT channels RocketIO serial transceivers capable of running 150 Mb/s to 6.5 Gb/s ...

Page 11

... N/A XC5VLX50 N/A 220 N/A XC5VLX85 N/A XC5VLX110 N/A XC5VLX155 XC5VLX220 XC5VLX330 XC5VLX20T 4 172 GTPs XC5VLX30T 4 GTPs 172 XC5VLX50T XC5VLX85T XC5VLX110T XC5VLX155T XC5VLX220T XC5VLX330T XC5VSX35T XC5VSX50T XC5VSX95T XC5VSX240T XC5VTX150T XC5VTX240T XC5VFX30T XC5VFX70T XC5VFX100T XC5VFX130T XC5VFX200T Notes: 1. Flip-chip packages are also available in Pb-Free versions (FFG). ...

Page 12

... Virtex-5 Family Overview Virtex-5 FPGA Ordering Information Virtex-5 FPGA ordering information shown in X-Ref Target - Figure 1 Example: XC5VLX50T-1FFG665C Device Type Speed Grade (-1, -2, -3 (1) ) Note speed grade is not available in all devices Revision History The following table shows the revision history for this document. ...

Page 13

R Notice of Disclaimer THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ...

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