XC5VLX50T-1FFG665C Xilinx Inc, XC5VLX50T-1FFG665C Datasheet - Page 6

FPGA, VIRTEX-5 LXT, 50K, 665FCBGA

XC5VLX50T-1FFG665C

Manufacturer Part Number
XC5VLX50T-1FFG665C
Description
FPGA, VIRTEX-5 LXT, 50K, 665FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG665C

No. Of Logic Blocks
7200
Family Type
Virtex-5
No. Of Speed Grades
1
Total Ram Bits
2211840
No. Of I/o's
360
Clock Management
DCM, PLL
I/o Supply Voltage
3.3V
Operating Frequency Max
550MHz
Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
665-BBGA, FCBGA
Core Supply Voltage Range
1V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
122-1565

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XC5VLX50T-1FFG665C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC5VLX50T-1FFG665C
Manufacturer:
XILINX
0
Part Number:
XC5VLX50T-1FFG665C
Manufacturer:
XILINX
Quantity:
500
Part Number:
XC5VLX50T-1FFG665C
Manufacturer:
XILINX
Quantity:
5 698
Part Number:
XC5VLX50T-1FFG665C
Quantity:
2 747
Part Number:
XC5VLX50T-1FFG665C
Quantity:
18
Part Number:
XC5VLX50T-1FFG665C
0
Part Number:
XC5VLX50T-1FFG665C4060
Manufacturer:
XILINX
Quantity:
1 122
Part Number:
XC5VLX50T-1FFG665C4060
Manufacturer:
XILINX
0
Part Number:
XC5VLX50T-1FFG665CES
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC5VLX50T-1FFG665CES
Quantity:
1 700
Virtex-5 Family Overview
Architectural Description
Virtex-5 FPGA Array Overview
Virtex-5 devices are user-programmable gate arrays with various configurable elements and embedded cores optimized for
high-density and high-performance system designs. Virtex-5 devices implement the following functionality:
6
I/O blocks provide the interface between package pins
and the internal configurable logic. Most popular and
leading-edge I/O standards are supported by
programmable I/O blocks (IOBs). The IOBs can be
connected to very flexible ChipSync logic for enhanced
source-synchronous interfacing. Source-synchronous
optimizations include per-bit deskew (on both input and
output signals), data serializers/deserializers, clock
dividers, and dedicated I/O and local clocking
resources.
Configurable Logic Blocks (CLBs), the basic logic
elements for Xilinx® FPGAs, provide combinatorial and
synchronous logic as well as distributed memory and
SRL32 shift register capability. Virtex-5 FPGA CLBs
are based on real 6-input look-up table technology and
provide superior capabilities and performance
compared to previous generations of programmable
logic.
Block RAM modules provide flexible 36 Kbit true dual-
port RAM that are cascadable to form larger memory
blocks. In addition, Virtex-5 FPGA block RAMs contain
optional programmable FIFO logic for increased device
utilization. Each block RAM can also be configured as
two independent 18 Kbit true dual-port RAM blocks,
providing memory granularity for designs needing
smaller RAM blocks.
Cascadable embedded DSP48E slices with 25 x 18
two’s complement multipliers and 48-bit
adder/subtracter/accumulator provide massively
parallel DSP algorithm support. In addition, each
DSP48E slice can be used to perform bitwise logical
functions.
Clock Management Tile (CMT) blocks provide the most
flexible, highest-performance clocking for FPGAs. Each
CMT contains two Digital Clock Manager (DCM) blocks
(self-calibrating, fully digital), and one PLL block (self-
calibrating, analog) for clock distribution delay
compensation, clock multiplication/division, coarse-
/fine-grained clock phase shifting, and input clock jitter
filtering.
www.xilinx.com
Additionally, LXT, SXT, TXT, and FXT devices also contain:
LXT and SXT devices contain:
TXT and FXT devices contain:
FXT devices contain:
The general routing matrix (GRM) provides an array of
routing switches between each internal component. Each
programmable element is tied to a switch matrix, allowing
multiple connections to the general routing matrix. The
overall programmable interconnection is hierarchical and
designed to support high-speed designs. In Virtex-5
devices, the routing connections are optimized to support
CLB interconnection in the fewest number of “hops.”
Reducing hops greatly increases post place-and-route
(PAR) design performance.
All programmable elements, including the routing
resources, are controlled by values stored in static storage
elements. These values are loaded into the FPGA during
configuration and can be reloaded to change the functions
of the programmable elements.
Integrated Endpoint blocks for PCI Express designs
providing x1, x4, or x8 PCI Express Endpoint
functionality. When used in conjunction with RocketIO
transceivers, a complete PCI Express Endpoint can be
implemented with minimal FPGA logic utilization.
10/100/1000 Mb/s Ethernet media-access control
blocks offer Ethernet capability.
RocketIO GTP transceivers capable of running up to
3.75 Gb/s. Each GTP transceiver supports full-duplex,
clock-and-data recovery.
GTX transceivers capable of running up to 6.5 Gb/s.
Each GTX transceiver supports full-duplex, clock-and-
data recovery.
Embedded IBM PowerPC 440 RISC CPUs. Each
PowerPC 440 CPU is capable of running up to
550 MHz. Each PowerPC 440 CPU also has an APU
(Auxiliary Processor Unit) interface that supports
hardware acceleration, and an integrated cross-bar for
high data throughput.
DS100 (v5.0) February 6, 2009
Product Specification
R

Related parts for XC5VLX50T-1FFG665C