XC5VLX50T-1FFG665C Xilinx Inc, XC5VLX50T-1FFG665C Datasheet - Page 115

• Manufacturer Part Number: XC5VLX50T-1FFG665C
• Description: FPGA, VIRTEX-5 LXT, 50K, 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG665C

• No. Of Logic Blocks: 7200
• Family Type: Virtex-5
• No. Of Speed Grades: 1
• Total Ram Bits: 2211840
• No. Of I/o's: 360
• Clock Management: DCM, PLL
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 550MHz
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 665-BBGA, FCBGA
• Core Supply Voltage Range: 1V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1565

Block RAM Introduction
Synchronous Dual-Port and Single-Port RAMs
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Data Flow
Table 4-1: Parity Use Sceneries (Continued)
In addition to distributed RAM memory and high-speed SelectIO™ memory interfaces,
Virtex-5 devices feature a large number of 36 Kb block RAMs. Each 36 Kb block RAM
contains two independently controlled 18 Kb RAMs. Block RAMs are placed in columns,
and the total number of block RAM memory depends on the size of the Virtex-5 device.
The 36 Kb blocks are cascadable to enable a deeper and wider memory implementation,
with a minimal timing penalty.
Embedded dual- or single-port RAM modules, ROM modules, synchronous FIFOs, and
data width converters are easily implemented using the Xilinx CORE Generator™ block
memory modules. Multirate FIFOs can be generated using the CORE Generator FIFO
Generator module. The synchronous or asynchronous (multirate) FIFO implementation
does not require additional CLB resources for the FIFO control logic since it uses dedicated
hardware resources.
The true dual-port 36 Kb block RAM dual-port memories consist of a 36 Kb storage area
and two completely independent access ports, A and B. Similarly, each 18 Kb block RAM
dual-port memory consists of an 18 Kb storage area and two completely independent
access ports, A and B. The structure is fully symmetrical, and both ports are
interchangeable.
names and descriptions.
Data can be written to either or both ports and can be read from either or both ports. Each
write operation is synchronous, each port has its own address, data in, data out, clock,
clock enable, and write enable. The read and write operations are synchronous and require
a clock edge.
There is no dedicated monitor to arbitrate the effect of identical addresses on both ports. It
is up to the user to time the two clocks appropriately. Conflicting simultaneous writes to
the same location never cause any physical damage but can result in data uncertainty.
Notes:
1. Do not use parity bits DIP/DOP when one port widths is less than nine and another port width is nine
RAMB36
RAMB36
RAMB36
RAMB36
Primitive
or greater.
Read Width
9, 18, or 36
9, 18, or 36
1, 2, or 4
1, 2, or 4
Figure 4-1
Settings
www.xilinx.com
illustrates the true dual-port data flow.
Write Width
9, 18, or 36
9, 18, or 36
1, 2, or 4
1, 2, or 4
Effective Read Width Effective Write Width
Same as setting
Same as setting
Same as setting
8, 16, or 32
Block RAM Introduction
Table 4-2
Same as setting
Same as setting
Same as setting
8, 16, or 32
lists the port
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