XC5VLX50T-1FFG665C Xilinx Inc, XC5VLX50T-1FFG665C Datasheet - Page 119

• Manufacturer Part Number: XC5VLX50T-1FFG665C
• Description: FPGA, VIRTEX-5 LXT, 50K, 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG665C

• No. Of Logic Blocks: 7200
• Family Type: Virtex-5
• No. Of Speed Grades: 1
• Total Ram Bits: 2211840
• No. Of I/o's: 360
• Clock Management: DCM, PLL
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 550MHz
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 665-BBGA, FCBGA
• Core Supply Voltage Range: 1V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1565

Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Conflict Avoidance
Asynchronous Clocking
Synchronous Clocking
X-Ref Target - Figure 4-4
Virtex-5 FPGA block RAM memory is a true dual-port RAM where both ports can access
any memory location at any time. When accessing the same memory location from both
ports, the user must, however, observe certain restrictions. There are two fundamentally
different situations: The two ports either have a common clock (synchronous clocking), or
the clock frequency and phase is different for the two ports (asynchronous clocking).
Asynchronous clocking is the more general case, where the active edges of both clocks do
not occur simultaneously:
•
•
Synchronous clocking is the special case, where the active edges of both port clocks occur
simultaneously:
•
•
•
There are no timing constraints when both ports perform a read operation.
When one port performs a write operation, the other port must not read- or write-
access the same memory location. The simulation model will produce an error if this
condition is violated. If this restriction is ignored, a read or write operation will
produce unpredictable results. There is, however, no risk of physical damage to the
device. If a read and write operation is performed, then the write will store valid data
at the write location.
There are no timing constraints when both ports perform a read operation.
When one port performs a write operation, the other port must not write into the
same location, unless both ports write identical data.
When one port performs a write operation, the write operation succeeds; the other
port can reliably read data from the same location if the write port is in READ_FIRST
mode. DATA_OUT on both ports will then reflect the previously stored data.
If the write port is in either WRITE_FIRST or in NO_CHANGE mode, then the DATA-
OUT on the read port would become invalid (unreliable). The mode setting of the
read-port does not affect this operation.
ADDR
CLK
WE
DO
EN
DI
Disable
0000
Figure 4-4: NO_CHANGE Mode Waveforms
XXXX
www.xilinx.com
aa
Read
MEM(aa)
Synchronous Dual-Port and Single-Port RAMs
1111
bb
MEM(bb)=1111
Write
2222
cc
MEM(cc)=2222
Write
dd
ug190_4_05_032206
XXXX
Read
MEM(dd)
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