XC5VLX50T-1FFG665C Xilinx Inc, XC5VLX50T-1FFG665C Datasheet - Page 122

• Manufacturer Part Number: XC5VLX50T-1FFG665C
• Description: FPGA, VIRTEX-5 LXT, 50K, 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG665C

• No. Of Logic Blocks: 7200
• Family Type: Virtex-5
• No. Of Speed Grades: 1
• Total Ram Bits: 2211840
• No. Of I/o's: 360
• Clock Management: DCM, PLL
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 550MHz
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 665-BBGA, FCBGA
• Core Supply Voltage Range: 1V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1565

Chapter 4: Block RAM
122
Cascadable Block RAM
Byte-wide Write Enable
In the Virtex-5 block RAM architecture, two 32K x 1 RAMs can be combined to form one
64K x 1 RAM without using local interconnect or additional CLB logic resources. Any two
adjacent block RAMs can be cascaded to generate a 64K x 1 block RAM. Increasing the
depth of the block RAM by cascading two block RAMs is available only in the 64K x 1
mode. Further information on cascadable block RAM is described in the
RAMB18 and RAMB36 Primitive Design Considerations
deeper sizes, consult the
block RAM with the appropriate ports connected in the Cascadable mode.
X-Ref Target - Figure 4-7
The byte-wide write enable feature of the block RAM gives the capability to write eight bit
(one byte) portions of incoming data. There are four independent byte-wide write enable
inputs to the RAMB36 true dual-port RAM. There are eight independent byte-wide write
enable inputs to block RAM in simple dual-port mode (RAMB36SDP).
summarizes the byte-wide write enables for the 36K and 18K block RAM. Each byte-wide
write enable is associated with one byte of input data and one parity bit. All byte-wide
write enable inputs must be driven in all data width configurations. This feature is useful
when using block RAM to interface with a microprocessor. Byte-wide write enable is not
available in the multirate FIFO or ECC mode. Byte-wide write enable is further described
in the
Figure 4-8
Table 4-4: Available Byte-wide Write Enables
Interconnect
RAMB36
RAMB36SDP
Primitive
Additional RAMB18 and RAMB36 Primitive Design Considerations
WE[3:0]
WE[3:0]
A[14:0]
A[14:0]
A15
A15
DI
DI
shows the byte-wide write-enable timing diagram for the RAMB36.
Block RAM
RAM_EXTENSION =
RAM_EXTENSION =
LOWER(1)
UPPER(0)
Maximum Bit Width
0
1
0
1
Creating Larger RAM Structures
Figure 4-7: Cascadable Block RAM
www.xilinx.com
36
72
D Q
D Q
D Q
D Q
D Q
D Q
D Q
D Q
DI
A[14:0]
A15
WE
DI
A[14:0]
A15
WE
Number of Byte-wide Write Enables
D0
D0
section. For other wider and/or
Optional
Output FF
Optional
Output FF
section.
Connect to logic High or Low
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
4
8
CASCADEOUT
Figure 4-7
(No Connect)
CASCADEIN
Table 4-4
CASCADEIN of Top
CASCADEOUT of Bottom
Additional
section.
1
0
1
0
shows the
ug190_4_07_071607
D0
D0
Not Used