XC5VLX50T-1FFG665C Xilinx Inc, XC5VLX50T-1FFG665C Datasheet - Page 124

• Manufacturer Part Number: XC5VLX50T-1FFG665C
• Description: FPGA, VIRTEX-5 LXT, 50K, 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG665C

• No. Of Logic Blocks: 7200
• Family Type: Virtex-5
• No. Of Speed Grades: 1
• Total Ram Bits: 2211840
• No. Of I/o's: 360
• Clock Management: DCM, PLL
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 550MHz
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 665-BBGA, FCBGA
• Core Supply Voltage Range: 1V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1565

Chapter 4: Block RAM
124
Figure 4-9
(RAMB36).
X-Ref Target - Figure 4-9
Table 4-5: Virtex-5 FPGA Block RAM, FIFO, Simple Dual Port, and ECC Primitives
Notes:
1. All eight primitives are described in the software Libraries guide as well as the language templates.
RAMB36
RAMB36SDP
FIFO36
FIFO36_72
RAMB18
RAMB18SDP
FIFO18
FIFO18_36
Primitive
illustrates all the I/O ports of the 36 Kb true dual-port block RAM primitive
Table 4-5
Supports port widths of x1, x2, x4, x9, x18, x36
Simple dual port (port width x72) and 64-bit ECC primitive (see
Figure
Supports port widths of x4, x9, x18, x36
FIFO (port width x72), optional ECC support
Supports port widths of x1, x2, x4, x9, x18
Simple dual port (port width x36)
Supports port widths of x4, x9, x18
FIFO (port width x36)
Figure 4-9: Block RAM Port Signals (RAMB36)
lists these primitives.
CASCADEOUTREGA
CASCADEOUTLATA
32
16
32
16
CASCADEINREGA
www.xilinx.com
4
4
4
4
4-29)
CASCADEINLATA
DIA
DIPA
ADDRA
WEA
ENA
REGCEA
SSRA
DIB
DIPB
ADDRB
WEB
ENB
REGCEB
SSRB
CLKA
CLKB
CASCADEINLATB
CASCADEINREGB
Description
CASCADEOUTLATB
CASCADEOUTREGB
DOPA
DOPB
DOA
DOB
ug0190_4_10_100906
32
32
4
4
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010