XC5VLX50T-1FFG665C Xilinx Inc, XC5VLX50T-1FFG665C Datasheet - Page 134

• Manufacturer Part Number: XC5VLX50T-1FFG665C
• Description: FPGA, VIRTEX-5 LXT, 50K, 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG665C

• No. Of Logic Blocks: 7200
• Family Type: Virtex-5
• No. Of Speed Grades: 1
• Total Ram Bits: 2211840
• No. Of I/o's: 360
• Clock Management: DCM, PLL
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 550MHz
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 665-BBGA, FCBGA
• Core Supply Voltage Range: 1V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1565

Chapter 4: Block RAM
X-Ref Target - Figure 4-12
X-Ref Target - Figure 4-13
Block RAM Timing Model
134
RAMEN
DBRAM
RAMEN
DBRAM
REGCE
REGCE
SSR
SSR
CLK
CLK
SSR only sets/resets DO when REGCE is also High.
DO
DO
Figure 4-13: SSR Operation in Register Mode with Variable REGCE
Figure 4-12: SSR Operation in Register Mode with REGCE High
This section describes the timing parameters associated with the block RAM in Virtex-5
devices (illustrated in
FPGA Data Sheet and the Timing Analyzer (TRCE) report from Xilinx software are also
available for reference.
D0
D0
Block RAM can be read when SSR is active.
D0
D0
Data appears on the output of the next REGCE.
Figure
www.xilinx.com
SRVAL
SRVAL
D1
D1
4-14). The switching characteristics section in the Virtex-5
D1
D1
SRVAL
D2
D2
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
ug190_4_29_071607
ug190_4_29_071607
D2
D3
D3
D2