XC5VLX50T-1FFG665C Xilinx Inc, XC5VLX50T-1FFG665C Datasheet - Page 141

• Manufacturer Part Number: XC5VLX50T-1FFG665C
• Description: FPGA, VIRTEX-5 LXT, 50K, 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG665C

• No. Of Logic Blocks: 7200
• Family Type: Virtex-5
• No. Of Speed Grades: 1
• Total Ram Bits: 2211840
• No. Of I/o's: 360
• Clock Management: DCM, PLL
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 550MHz
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 665-BBGA, FCBGA
• Core Supply Voltage Range: 1V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1565

Table 4-13: FIFO Capacity
Table 4-14: Comparison of Synchronous FIFO Implementations
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Synchronous FIFO Implementations
4k + 1 entries by 4 bits
2k + 1 entries by 9 bits
1k + 1 entries by 18 bits
512 + 1 entries by 36 bits
EN_SYN = TRUE, DO_REG = 0
EN_SYN = TRUE, DO_REG = 1
EN_SYN = FALSE, DO_REG = 1
RDCLK = WRCLK
18 Kb FIFO
Synchronous FIFO Implementations
Standard Mode
Table 4-14
timing differences.
X-Ref Target - Figure 4-16
8k + 1 entries by 4 bits
4k + 1 entries by 9 bits
2k + 1 entries by 18 bits
512 + 1 entries by 72 bits
1k + 1 entries by 36 bits
EN_SYN = FALSE
EN_SYN = TRUE
EN_SYN = TRUE
36 Kb FIFO
outlines varied implementations of synchronous FIFOs.
DO_REG = 0
DO_REG = 1
DO_REG = 1
No flag uncertainty
Faster clock-to-out signals, no
flag uncertainty
Faster clock-to-out signals.
Similar to a Virtex-4 FIFO.
Figure 4-16: Synchronous FIFO Data Timing Diagram
rdclk
rden
DO
DO
DO
Advantages
www.xilinx.com
4k + 2 entries by 4 bits
2k + 2 entries by 9 bits
1k + 2 entries by 18 bits
512 + 2 entries by 36 bits
18 Kb FIFO
Longer clock-to-out signals
Data Latency increased by one. Behaves
like a synchronous FIFO with an extra data
output pipeline register
Falling-edge flag uncertainty. Rising-edge
guaranteed on FULL and EMPTY
FWFT Mode
T
CKO
= 1.9ns
8k + 2 entries by 4 bits
4k + 2 entries by 9 bits
2k + 2 entries by 18 bits
1k + 2 entries by 36 bits
512 + 2 entries by 72 bits
Disadvantages
Built-in FIFO Support
Figure 4-16
36 Kb FIFO
ug190_c4_x1_071007
shows the
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