XC5VLX50T-1FFG665C Xilinx Inc, XC5VLX50T-1FFG665C Datasheet - Page 153

• Manufacturer Part Number: XC5VLX50T-1FFG665C
• Description: FPGA, VIRTEX-5 LXT, 50K, 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG665C

• No. Of Logic Blocks: 7200
• Family Type: Virtex-5
• No. Of Speed Grades: 1
• Total Ram Bits: 2211840
• No. Of I/o's: 360
• Clock Management: DCM, PLL
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 550MHz
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 665-BBGA, FCBGA
• Core Supply Voltage Range: 1V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1565

Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Clock Event 1: Write Operation and Assertion of Almost FULL Signal
During a write operation to an almost full FIFO, the Almost FULL signal is asserted.
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Clock Event 2: Write Operation, and Assertion of FULL Signal
The FULL signal pin is asserted when the FIFO is full.
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If the FIFO is full, and a read followed by a write is performed, the FULL signal remains
asserted.
Clock Event 3: Write Operation and Assertion of Write Error Signal
The write error signal pin is asserted when data going into the FIFO is not written because
the FIFO is in a Full state.
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Clock Event 4: Write Operation and Deassertion of Write Error Signal
The write error signal pin is deasserted when a user stops trying to write into a full FIFO.
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The write error signal is asserted/deasserted at every write-clock positive edge. As long as
both the write enable and Full signals are true, write error will remain asserted.
At time T
inputs of the FIFO.
At time T
the WREN input of the FIFO.
At time T
asserted at the AFULL output pin of the FIFO.
At time T
inputs of the FIFO.
Write enable remains asserted at the WREN input of the FIFO.
At time T
pin of the FIFO.
At time T
inputs of the FIFO.
Write enable remains asserted at the WREN input of the FIFO.
At time T
WRERR output pin of the FIFO. Data 05 is not written into the FIFO.
At time T
WREN input of the FIFO.
At time T
WRERR output pin of the FIFO.
FDCK_DI
FCCK_WREN
FCKO_AFULL
FDCK_DI
FCKO_FULL
FDCK_DI
FCKO_WRERR
FCCK_WREN
FCKO_WRERR
, before clock event 1 (WRCLK), data 00 becomes valid at the DI
, before clock event 2 (WRCLK), data 04 becomes valid at the DI
, before clock event 3 (WRCLK), data 05 becomes valid at the DI
, after clock event 2 (WRCLK), Full is asserted at the FULL output
, before clock event 1 (WRCLK), write enable becomes valid at
, before clock event 4 (WRCLK), write enable is deasserted at the
, one clock cycle after clock event 1 (WRCLK), Almost Full is
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, after clock event 3 (WRCLK), a write error is asserted at the
, after clock event 4 (WRCLK), write error is deasserted at the
FIFO Timing Models and Parameters
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