XC5VLX50T-1FFG665C Xilinx Inc, XC5VLX50T-1FFG665C Datasheet - Page 163

• Manufacturer Part Number: XC5VLX50T-1FFG665C
• Description: FPGA, VIRTEX-5 LXT, 50K, 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG665C

• No. Of Logic Blocks: 7200
• Family Type: Virtex-5
• No. Of Speed Grades: 1
• Total Ram Bits: 2211840
• No. Of I/o's: 360
• Clock Management: DCM, PLL
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 550MHz
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 665-BBGA, FCBGA
• Core Supply Voltage Range: 1V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1565

Table 4-22: FIFO ECC Port Names and Descriptions
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Notes:
1. Hamming code implemented in the FIFO ECC logic detects one of three conditions: no detectable error, single-bit error detected and
DI[63:0]
DIP[7:0]
WREN
RDEN
RST
WRCLK
RDCLK
DO[63:0]
DOP[7:0]
SBITERR
DBITERR
ECCPARITY[7:0]
FULL
ALMOSTFULL
EMPTY
ALMOSTEMPTY
RDCOUNT
WRCOUNT
WRERR
RDERR
corrected on DO (but not corrected in the memory), and double-bit error detected without correction. SBITERR and DBITERR
indicate these three conditions.
Port Name
(1)
(1)
Direction
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Table 4-22
Data input bus.
Data input parity bus. Not used when standard mode is used.
Write enable. When WREN = 1, data will be written into memory. When WREN = 0,
write is disabled
Read enable. When RDEN = 1, data will be read from memory. When RDEN = 0, read
is disabled.
Asynchronous reset of FIFO counter and flags. Reset must be asserted for three clock
cycles. Reset does not affect DO or ECC signals.
Clock for write operations.
Clock for read operations.
Data output bus.
Data output parity bus.
Single-bit error status.
Double-bit error status.
ECC encoder output bus.
FIFO FULL flag.
FIFO ALMOSTFULL flag.
FIFO EMPTY flag.
The FIFO data read pointer.
The FIFO data write pointer.
When the FIFO is full, any additional write operation generates an error flag.
When the FIFO is empty, any additional read operation generates an error flag.
FIFO ALMOSTEMPTY flag.
lists and describes the FIFO ECC I/O port names.
www.xilinx.com
Signal Description
Built-in Error Correction
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