XC5VLX50T-1FFG665C Xilinx Inc, XC5VLX50T-1FFG665C Datasheet - Page 2

• Manufacturer Part Number: XC5VLX50T-1FFG665C
• Description: FPGA, VIRTEX-5 LXT, 50K, 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG665C

• No. Of Logic Blocks: 7200
• Family Type: Virtex-5
• No. Of Speed Grades: 1
• Total Ram Bits: 2211840
• No. Of I/o's: 360
• Clock Management: DCM, PLL
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 550MHz
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 665-BBGA, FCBGA
• Core Supply Voltage Range: 1V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1565

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Revision History
The following table shows the revision history for this document.
Virtex-5 FPGA User Guide
04/14/06
05/12/06
7/19/06
Date
Version
1.0
1.1
1.2
Initial Xilinx release.
Minor typographical edits and clarifications.
Chapter 1: Revised
Chapter 2: Revised
primitive. Removed outdated clocking wizard section
Chapter 3: Revised
and
Chapter 4: Added a note to
design rules on
Chapter 5: Added
Chapter 6: Updated
Chapter 7: Revised
Chapter 8: Revised
Chapter 1: Revised
Changed the P and N I/O designations in
Chapter 4: Added
Top-Level View, page
Chapter 6: Minor clarification edits. Changed to N/A from unused in
Table
Chapter 7: Minor edits to clarify IODELAY in this chapter.
Chapter 8: Small clarifications in
Figure
6-37, and
3-12. Added
Table
page
Block RAM SSR in Register Mode, page 133
Figure 5-7
ILOGIC Resources, page 318
Figure
Figure 2-2
Figure
Table
Global Clock Buffers, page 27
Simultaneous Switching Output Limits
www.xilinx.com
132.
6-38.
142. Revised the FIFO operations
PLL in Virtex-4 FPGA PMCD Legacy Mode
8-1.
1-21.
3-1,
Table 4-5, page
and
and
Figure
ISERDES_NODELAY Ports, page
Figure
Figure
3-2,
Revision
5-11, revised
2-4. Removed reference to a DCM_PS
Table
Figure
124. Clarified the RAMB36 port mapping
3-2,
including
to clarify single-ended clock pins.
1-19.
Table
Figure 5-32
page
Reset, page 144
3-4,
Figure
83.
section.
UG190 (v5.3) May 17, 2010
Figure
and
for clarity.
7-1. Revised
FIFO Architecture: a
355.
section.
3-9,
Table
description.
Equation
6-36,
Table
3-8,
7-3.