XC5VLX50T-1FFG665C Xilinx Inc, XC5VLX50T-1FFG665C Datasheet - Page 203

• Manufacturer Part Number: XC5VLX50T-1FFG665C
• Description: FPGA, VIRTEX-5 LXT, 50K, 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG665C

• No. Of Logic Blocks: 7200
• Family Type: Virtex-5
• No. Of Speed Grades: 1
• Total Ram Bits: 2211840
• No. Of I/o's: 360
• Clock Management: DCM, PLL
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 550MHz
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 665-BBGA, FCBGA
• Core Supply Voltage Range: 1V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1565

Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Timing Characteristics
Figure 5-26
X-Ref Target - Figure 5-26
•
•
•
At time T
CE input of the slice register.
At time T
become valid-High at the D input of the slice register and is reflected on either the
AQ, BQ, CQ, or DQ pin at time T
At time T
becomes valid-High, resetting the slice register. This is reflected on the AQ, BQ, CQ,
or DQ pin at time T
illustrates the general timing characteristics of a Virtex-5 FPGA slice.
CEO
DICK
SRCK
AQ/BQ/CQ/DQ
AX/BX/CX/DX
before clock event (1), the clock-enable signal becomes valid-High at the
SR (RESET)
Figure 5-26: General Slice Timing Characteristics
before clock event (1), data from either AX, BX, CX, or DX inputs
before clock event (3), the SR signal (configured as synchronous reset)
(DATA)
(OUT)
CKO
CLK
CE
www.xilinx.com
after clock event (3).
1
CKO
T
T
CEO
DICK
after clock event (1).
T
CKO
2
3
CLB / Slice Timing Models
T
ug190_5_26_050506
SRCK
T
CKO
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