XC5VLX50T-1FFG665C Xilinx Inc, XC5VLX50T-1FFG665C Datasheet - Page 25

• Manufacturer Part Number: XC5VLX50T-1FFG665C
• Description: FPGA, VIRTEX-5 LXT, 50K, 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG665C

• No. Of Logic Blocks: 7200
• Family Type: Virtex-5
• No. Of Speed Grades: 1
• Total Ram Bits: 2211840
• No. Of I/o's: 360
• Clock Management: DCM, PLL
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 550MHz
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 665-BBGA, FCBGA
• Core Supply Voltage Range: 1V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1565

Clock Resources
Global and Regional Clocks
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Global Clocks
Regional Clocks and I/O Clocks
For clocking purposes, each Virtex®-5 device is divided into regions. The number of
regions varies with device size, eight regions in the smallest device to 24 regions in the
largest one. Global I/O and regional clocking resources manage complex and simple
clocking requirements. Non-clock resources, such as local routing, are not recommended
when performing clock functions.
Each Virtex-5 device has 32 global clock lines that can clock all sequential resources on the
whole device (CLB, block RAM, CMTs, and I/O), and also drive logic signals. Any ten of
these 32 global clock lines can be used in any region. Global clock lines are only driven by
a global clock buffer, which can also be used as a clock enable circuit, or a glitch-free
multiplexer. It can select between two clock sources, and can also switch away from a
failed clock source.
A global clock buffer is often driven by a Clock Management Tile (CMT) to eliminate the
clock distribution delay, or to adjust its delay relative to another clock. There are more
global clocks than CMTs, but a CMT often drives more than one global clock.
Each region has two regional clock buffers and four regional clock trees. A Virtex-5 I/O
bank spans exactly one region with the exception of some banks in the center column. Each
bank with the size identical to a region contains four clock-capable clock inputs. Each of
these inputs can differentially or single-endedly drive four I/O clocks and two regional
clocks in the same bank or region. In addition, regional clocks can drive regional clock trees
in the adjacent regions. When the clock-capable I/Os are driven by single-ended clocks,
then the clock must be connected to the positive (P) side of the differential “clock capable”
pin pair. The negative (N) side can be used as a general purpose I/O or left unconnected.
The regional clock buffer can be programmed to divide the incoming clock rate by any
integer number from 1 to 8. This feature, in conjunction with the programmable
serializer/deserializer in the IOB, (see
allows source-synchronous systems to cross clock domains without using additional logic
resources.
A third type of clocking resource, I/O clocks, are very fast and serve localized I/O
serializer/deserializer circuits. See
www.xilinx.com
Chapter 8, Advanced SelectIO Logic
Chapter 8, Advanced SelectIO Logic
Chapter 1
Resources.
Resources),
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