XC5VLX50T-1FFG665C Xilinx Inc, XC5VLX50T-1FFG665C Datasheet - Page 274

FPGA, VIRTEX-5 LXT, 50K, 665FCBGA

XC5VLX50T-1FFG665C

Manufacturer Part Number
XC5VLX50T-1FFG665C
Description
FPGA, VIRTEX-5 LXT, 50K, 665FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG665C

No. Of Logic Blocks
7200
Family Type
Virtex-5
No. Of Speed Grades
1
Total Ram Bits
2211840
No. Of I/o's
360
Clock Management
DCM, PLL
I/o Supply Voltage
3.3V
Operating Frequency Max
550MHz
Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
665-BBGA, FCBGA
Core Supply Voltage Range
1V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
122-1565

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Chapter 6: SelectIO Resources
274
HSTL Class I (1.2V)
SSTL (Stub-Series Terminated Logic)
Figure 6-66
Class I (1.2V). It is used for unidirectional links.
X-Ref Target - Figure 6-66
Table 6-21
Table 6-27: HSTL Class I (1.2V) DC Voltage Specifications
The Stub-Series Terminated Logic (SSTL) for 2.5V (SSTL2) and 1.8V (SSTL18) standards are
for general purpose memory buses. SSTL2 is defined by the JEDEC standard JESD8-9B and
SSTL18 is defined by the JEDEC standard JESD8-15. The SSTL2 standard has two classes;
Class I is for unidirectional and class II is for bidirectional signaling. Virtex-5 FPGA I/O
supports both standards for single-ended signaling and differential signaling. This
standard requires a differential amplifier input buffer and a push-pull output buffer.
Notes:
1. V
2. Per EIA/JESD8-6, “The value of V
V
V
V
V
V
V
V
I
I
OH
OL
CCO
REF
TT
IH
IL
OH
OL
the use conditions specified by the user.”
OL
at V
at V
(2)
and V
External Termination
OL
OH
lists the HSTL Class I (1.2V) DC voltage specifications.
(mA)
shows a sample circuit illustrating a valid termination technique for HSTL
HSTL_I_12
OH
(mA)
for lower drive currents are sample tested.
(1)
(1)
IOB
Figure 6-66: HSTL Class I (1.2V) Termination
www.xilinx.com
REF
Z 0
R P = Z 0 = 50Ω
is to be selected by the user to provide optimum noise margin in
V
V
V
CCO
CCO
REF
V
TT
Min
1.14
–6.3
6.3
– .0.315
= 0.6V
+ 0.08
× 0.48
IOB
V
REF
V
CCO
= 0.6V
Typ
1.2
0.6
× 0.5
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
HSTL_I_12
+
ug190_6_62_030306
V
V
CCO
REF
0.315
Max
1.26
– 0.08
× 0.52

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