XC5VLX50T-1FFG665C Xilinx Inc, XC5VLX50T-1FFG665C Datasheet - Page 299

• Manufacturer Part Number: XC5VLX50T-1FFG665C
• Description: FPGA, VIRTEX-5 LXT, 50K, 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG665C

• No. Of Logic Blocks: 7200
• Family Type: Virtex-5
• No. Of Speed Grades: 1
• Total Ram Bits: 2211840
• No. Of I/o's: 360
• Clock Management: DCM, PLL
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 550MHz
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 665-BBGA, FCBGA
• Core Supply Voltage Range: 1V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1565

Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Table 6-39
Table 6-39: I/O Compatibility
LVTTL
LVCMOS33
LVDCI_33
HSLVDCI_33
PCIX
PCI33_3
PCI66_3
LVDS_25
LVDSEXT_25
HT_25
RSDS_25
BLVDS_25
LVPECL_25
SSTL2_I
SSTL2_II
DIFF_SSTL2_I
DIFF_SSTL2_II
LVCMOS25
LVDCI_25
HSLVDCI_25
LVDCI_DV2_25
SSTL2_I_DCI
SSTL2_II_DCI
SSTL2_II_T_DCI
DIFF_SSTL2_I_DCI
DIFF_SSTL2_II_DCI
I/O Standard
(1)
(1)
(1)
(1)
(4)
summarizes the Virtex-5 FPGA supported I/O standards.
(1)
(1)
(1)
www.xilinx.com
Output
3.3
2.5
V
Rules for Combining I/O Standards in the Same Bank
CCO
Note (2)
Input
3.3
2.5
V
V
Input
V
N/R
N/R
N/R
CCO
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
CCO
N/R
N/R
N/R
1.25
1.25
1.25
1.25
1.25
REF
/2
/2
Output
Series
Series
Series
Series
Series
Termination Type
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
Split
Split
Input
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
Split
Split
Split
Split
Split
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