XC5VLX50T-1FFG665C Xilinx Inc, XC5VLX50T-1FFG665C Datasheet - Page 322

• Manufacturer Part Number: XC5VLX50T-1FFG665C
• Description: FPGA, VIRTEX-5 LXT, 50K, 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG665C

• No. Of Logic Blocks: 7200
• Family Type: Virtex-5
• No. Of Speed Grades: 1
• Total Ram Bits: 2211840
• No. Of I/o's: 360
• Clock Management: DCM, PLL
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 550MHz
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 665-BBGA, FCBGA
• Core Supply Voltage Range: 1V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1565

Chapter 7: SelectIO Logic Resources
322
IDDR VHDL and Verilog Templates
ILOGIC Timing Models
ILOGIC Timing Characteristics
Table 7-4: IDDR Attributes
The Libraries Guide includes templates for instantiation of the IDDR primitive in VHDL
and Verilog.
This section describes the timing associated with the various resources within the ILOGIC
block.
Figure 7-6
T
X-Ref Target - Figure 7-6
Clock Event 1
•
•
DDR_CLK_EDGE
INIT_Q1
INIT_Q2
SRTYPE
CLK
CE1
IDOCKD
SR
Q1
Attribute Name
D
At time T
High at the CE1 input of the input register, enabling the input register for incoming
data.
At time T
input of the input register and is reflected on the Q1 output of the input register at
time T
.
illustrates ILOGIC register timing. When IDELAY is used, T
ICKQ
ICE1CK
IDOCK
Figure 7-6: ILOGIC Input Register Timing Characteristics
after Clock Event 1.
1
before Clock Event 1, the input signal becomes valid-High at the D
before Clock Event 1, the input clock enable signal becomes valid-
Sets the IDDR mode of operation with
respect to clock edge
Sets the initial value for Q1 port
Sets the initial value for Q2 port
Set/Reset type with respect to clock (C) ASYNC (default), SYNC
T
T
IDOCK
ICE1CK
www.xilinx.com
T
ICKQ
Description
2
3
OPPOSITE_EDGE (default),
SAME_EDGE,
SAME_EDGE_PIPELINED
0 (default), 1
0 (default), 1
4
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Possible Values
T
ISRCK
IDOCK
T
ICKQ
is replaced by
ug190_7_06_041206
5