XC5VLX50T-1FFG665C Xilinx Inc, XC5VLX50T-1FFG665C Datasheet - Page 323

• Manufacturer Part Number: XC5VLX50T-1FFG665C
• Description: FPGA, VIRTEX-5 LXT, 50K, 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG665C

• No. Of Logic Blocks: 7200
• Family Type: Virtex-5
• No. Of Speed Grades: 1
• Total Ram Bits: 2211840
• No. Of I/o's: 360
• Clock Management: DCM, PLL
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 550MHz
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 665-BBGA, FCBGA
• Core Supply Voltage Range: 1V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1565

Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
ILOGIC Timing Characteristics, DDR
Clock Event 4
•
Figure 7-7
used, T
OPPOSITE_EDGE mode. For other modes, add the appropriate latencies as shown in
Figure 7-4, page
X-Ref Target - Figure 7-7
Clock Event 1
•
•
Clock Event 2
•
Clock Event 9
•
Table 7-5
in the Virtex-5 FPGA Data Sheet.
(Reset)
Figure 7-7: ILOGIC in IDDR Mode Timing Characteristics (OPPOSITE_EDGE Mode)
CLK
CE1
T
SR
Q1
Q2
IDOCK
At time T
this case) becomes valid-High resetting the input register and reflected at the Q1
output of the IOB at time T
At time T
High at the CE1 input of both of the DDR input registers, enabling them for incoming
data. Since the CE1 and D signals are common to both DDR registers, care must be
taken to toggle these signals between the rising edges and falling edges of CLK as
well as meeting the register setup-time relative to both clocks.
At time T
valid-High at the D input of both registers and is reflected on the Q1 output of input
register 1 at time T
At time T
valid-Low at the D input of both registers and is reflected on the Q2 output of input
register 2 at time T
At time T
this case) becomes valid-High resetting Q1 at time T
at time T
D
T
IDOCK
ICKQ
describes the function and control signals of the ILOGIC switching characteristics
illustrates the ILOGIC in IDDR mode timing characteristics. When IDELAY is
ICKQ
ISRCK
ISRCK
ICE1CK
IDOCK
IDOCK
is replaced by T
1
321.
T
after Clock Event 10.
ICE1CK
before Clock Event 4, the SR signal (configured as synchronous reset in
before Clock Event 9, the SR signal (configured as synchronous reset in
before Clock Event 1 (rising edge of CLK), the input signal becomes
before Clock Event 2 (falling edge of CLK), the input signal becomes
before Clock Event 1, the input clock enable signal becomes valid-
2
T
ICKQ
ICKQ
IDOCK
www.xilinx.com
after Clock Event 1.
after Clock Event 2 (no change in this case).
3
IDOCKD
ICKQ
4
after Clock Event 4.
. The example shown uses IDDR in
5
T
ICKQ
6
7
ICKQ
after Clock Event 9, and Q2
8
9
ILOGIC Resources
10
T
T
ISRCK
ICKQ
UG190_7_07_041206
11
T
ICKQ
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