XC5VLX50T-1FFG665C Xilinx Inc, XC5VLX50T-1FFG665C Datasheet - Page 336

FPGA, VIRTEX-5 LXT, 50K, 665FCBGA

XC5VLX50T-1FFG665C

Manufacturer Part Number
XC5VLX50T-1FFG665C
Description
FPGA, VIRTEX-5 LXT, 50K, 665FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG665C

No. Of Logic Blocks
7200
Family Type
Virtex-5
No. Of Speed Grades
1
Total Ram Bits
2211840
No. Of I/o's
360
Clock Management
DCM, PLL
I/o Supply Voltage
3.3V
Operating Frequency Max
550MHz
Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
665-BBGA, FCBGA
Core Supply Voltage Range
1V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
122-1565

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Chapter 7: SelectIO Logic Resources
X-Ref Target - Figure 7-13
336
CLK
CLK
Q1
Q2
D1
D2
T1
T2
Figure 7-13: IODELAY and IOB in Output Mode when 3-state is Enabled
ODDR
ODDR
IDDR
The second case uses bidirectional IODELAY when the I/O is an input switching to an
output.
by the 3-state TSCONTROL signal coming from the ODDR T flip-flop. This controls the
selection of MUXes E and F for the output path and ODELAY_VALUE respectively.
Additionally, the OBUF changes to not being 3-stated and starts to drive the PAD.
Figure 7-13
DATAOUT
ODATAIN
IODELAY
shows the IOB and IODELAY moving toward the output mode as set
Delay
Chain
www.xilinx.com
TSCONTROL
MUX E
MUX F
T
ODELAY_VALUE
IDELAY_VALUE
ODATAIN
IDATAIN
OBUF
IBUF
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
IOB
IODELAY_04_082107
PAD

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