XC5VLX50T-1FFG665C Xilinx Inc, XC5VLX50T-1FFG665C Datasheet - Page 343

• Manufacturer Part Number: XC5VLX50T-1FFG665C
• Description: FPGA, VIRTEX-5 LXT, 50K, 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG665C

• No. Of Logic Blocks: 7200
• Family Type: Virtex-5
• No. Of Speed Grades: 1
• Total Ram Bits: 2211840
• No. Of I/o's: 360
• Clock Management: DCM, PLL
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 550MHz
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 665-BBGA, FCBGA
• Core Supply Voltage Range: 1V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1565

Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
X-Ref Target - Figure 7-20
Instantiating IDELAYCTRL With and Without LOC Constraints
There are cases where the user instantiates an IDELAYCTRL module with a LOC
constraint but also instantiates an IDELAYCTRL module without a LOC constraint. In the
case where an IP Core is instantiated with a non-location constrained IDELAYCTRL
module and also wants to instantiate an IDELAYCTRL module without a LOC constraint
for another part of the design, the implementation tools will perform the following:
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The VHDL and Verilog use models for instantiating a mixed usage model are provided in
the Libraries Guide. In the example, a user is instantiating a non-location constrained
IDELAYCTRL instance with the RDY signal connected. This discussion is also valid when
the RDY signal is ignored.
The circuitry that results from instantiating the IDELAYCTRL components is illustrated in
Figure
Instantiate the LOC IDELAYCTRL instances as described in the section
IDELAYCTRL with Location (LOC)
Replicate the non-location constrained IDELAYCTRL instance to populate with an
IDELAYCTRL instance in every clock region without a location constrained
IDELAYCTRL instance in place.
The signals connected to the RST and REFCLK input ports of the non-location
constrained IDELAYCTRL instance are connected to the corresponding input ports of
the replicated IDELAYCTRL instances.
If the RDY port of the non-location constrained IDELAYCTRL instance is ignored,
then all the RDY signals of the replicated IDELAYCTRL instances are also ignored.
If the RDY port of the non-location constrained IDELAYCTRL instance is connected,
then the RDY port of the non-location constrained instance plus the RDY ports of the
replicated instances are connected to an auto-generated AND gate. The
implementation tools assign the signal name connected to the RDY port of the non-
location constrained instance to the output of the AND gate.
All the ports of the location constrained instances (RST, REFCLK, and RDY) are
independent from each other and from the replicated instances.
7-21.
Figure 7-20: Instantiate IDELAYCTRL with LOC Constraint
REFCLK
www.xilinx.com
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rst_1
rst_2
rst_n
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REFCLK
RST
REFCLK
RST
REFCLK
RST
Input/Output Delay Element (IODELAY)
IDELAYCTRL_1
IDELAYCTRL_2
IDELAYCTRL_n
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RDY
RDY
RDY
ug190_7_15_041306
rdy_1
rdy_2
rdy_n
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Instantiating
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