XC5VLX50T-1FFG665C Xilinx Inc, XC5VLX50T-1FFG665C Datasheet - Page 356

• Manufacturer Part Number: XC5VLX50T-1FFG665C
• Description: FPGA, VIRTEX-5 LXT, 50K, 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG665C

• No. Of Logic Blocks: 7200
• Family Type: Virtex-5
• No. Of Speed Grades: 1
• Total Ram Bits: 2211840
• No. Of I/o's: 360
• Clock Management: DCM, PLL
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 550MHz
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 665-BBGA, FCBGA
• Core Supply Voltage Range: 1V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1565

Chapter 8: Advanced SelectIO Logic Resources
356
Bitslip Operation - BITSLIP
Clock Enable Inputs - CE1 and CE2
X-Ref Target - Figure 8-3
The BITSLIP pin performs a Bitslip operation synchronous to CLKDIV when asserted
(active High). Subsequently, the data seen on the Q1 to Q6 output ports will shift, as in a
barrel-shifter operation, one position every time Bitslip is invoked (DDR operation is
different from SDR). See
Each ISERDES_NODELAY block contains an input clock enable module
X-Ref Target - Figure 8-4
When NUM_CE = 1, the CE2 input is not used, and the CE1 input is an active High clock
enable connected directly to the input registers in the ISERDES_NODELAY. When
NUM_CE = 2, the CE1 and CE2 inputs are both used, with CE1 enabling the
ISERDES_NODELAY for ½ of a CLKDIV cycle, and CE2 enabling the
ISERDES_NODELAY for the other ½. The internal clock enable signal ICE shown in
Figure 8-4
Data Bits
CLKDIV_TX
Figure 8-3: Bit Ordering on Q1–Q6 Outputs of ISERDES_NODELAY Ports
CLKDIV
CLKDIV
C
D
A
B
E
F
RST
RST
CE1
CE2
is derived from the CE1 and CE2 inputs. ICE drives the clock enable inputs of
D1
D2
D3
D4
D5
D6
OSERDES
D
AR
D
AR
Figure 8-4: Input Clock Enable Module
BITSLIP Submodule
Q
www.xilinx.com
Q
Q
CE1R
CE2R
CLK_TX
F
E
D
for more details.
C
B
NUM_CE
CLK_RX
1
2
2
A
ICE
(To ISERDES Input Registers)
CLKDIV
D
ISERDES
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
X
0
1
Q1
Q2
Q3
Q4
Q5
Q6
UG190_8_04_110707
(Figure
CE2R
CE1R
CLKDIV_RX
UG190_8_03_100307
CE1
ICE
8-4).
E
D
C
B
A
F