XC5VLX50T-1FFG665C Xilinx Inc, XC5VLX50T-1FFG665C Datasheet - Page 358

• Manufacturer Part Number: XC5VLX50T-1FFG665C
• Description: FPGA, VIRTEX-5 LXT, 50K, 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG665C

• No. Of Logic Blocks: 7200
• Family Type: Virtex-5
• No. Of Speed Grades: 1
• Total Ram Bits: 2211840
• No. Of I/o's: 360
• Clock Management: DCM, PLL
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 550MHz
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 665-BBGA, FCBGA
• Core Supply Voltage Range: 1V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1565

Chapter 8: Advanced SelectIO Logic Resources
Table 8-2: ISERDES_NODELAY Attributes
358
BITSLIP_ENABLE
DATA_RATE
DATA_WIDTH
INTERFACE_TYPE
NUM_CE
SERDES_MODE
Attribute Name
ISERDES_NODELAY Attributes
BITSLIP_ENABLE Attribute
DATA_RATE Attribute
Allows the user to use the Bitslip submodule
or bypass it. See
Enables incoming data stream to be
processed as SDR or DDR data. See
DATA_RATE
Defines the width of the serial-to-parallel
converter. The legal value depends on the
DATA_RATE attribute (SDR or DDR). See
DATA_WIDTH
Chooses the ISERDES_NODELAY use
model. See
Defines the number of clock enables. See
NUM_CE
Defines whether the ISERDES_NODELAY
module is a master or slave when using
width expansion. See
Attribute.
frequency domain. Therefore, RST should be driven High for a minimum of one CLKDIV
cycle.
When building an interface consisting of multiple ISERDES_NODELAY ports, all
ISERDES_NODELAY ports in the interface must be synchronized. The internal retiming of
the RST input is designed so that all ISERDES_NODELAY blocks that receive the same
reset pulse come out of reset synchronized with one another. The reset timing of multiple
ISERDES_NODELAY ports is shown in
Table 8-2
description of each attribute follows the table. For more information on applying these
attributes in UCF, VHDL, or Verilog code, refer to the Xilinx ISE Software Manual.
The BITSLIP_ENABLE attribute enables the Bitslip submodule. The possible values are
TRUE and FALSE (default). BITSLIP_ENABLE must be set to TRUE when
INTERFACE_TYPE is NETWORKING and FALSE when INTERFACE_TYPE is MEMORY.
When set to TRUE, the Bitslip submodule responds to the BITSLIP signal. When set to
FALSE, the Bitslip submodule is bypassed. See
The DATA_RATE attribute defines whether the incoming data stream is processed as
single data rate (SDR) or double data rate (DDR). The allowed values for this attribute are
SDR and DDR. The default value is DDR.
Attribute.
summarizes all the applicable ISERDES_NODELAY attributes. A detailed
INTERFACE_TYPE
Attribute.
BITSLIP_ENABLE
Attribute.
Description
SERDES_MODE
www.xilinx.com
Attribute.
Attribute.
Figure 8-9, page
Boolean: “TRUE” or “FALSE”
String: “SDR” or “DDR”
Integer: 2, 3, 4, 5, 6, 7, 8, or 10.
If DATA_RATE = DDR, value is
limited to 4, 6, 8, or 10.
If DATA_RATE = SDR, value is
limited to 2, 3, 4, 5, 6, 7, or 8.
String: “MEMORY” or
“NETWORKING”
Integer: 1 or 2
String: “MASTER” or “SLAVE”
BITSLIP
Submodule.
365.
Value
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
FALSE
DDR
4
MEMORY
2
MASTER
Default
Value