XC5VLX50T-1FFG665C Xilinx Inc, XC5VLX50T-1FFG665C Datasheet - Page 366

• Manufacturer Part Number: XC5VLX50T-1FFG665C
• Description: FPGA, VIRTEX-5 LXT, 50K, 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG665C

• No. Of Logic Blocks: 7200
• Family Type: Virtex-5
• No. Of Speed Grades: 1
• Total Ram Bits: 2211840
• No. Of I/o's: 360
• Clock Management: DCM, PLL
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 550MHz
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 665-BBGA, FCBGA
• Core Supply Voltage Range: 1V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1565

Chapter 8: Advanced SelectIO Logic Resources
366
BITSLIP Submodule
Bitslip Operation
All ISERDES blocks in Virtex-5 devices contain a Bitslip submodule. This submodule is
used for word-alignment purposes in source-synchronous networking-type applications.
Bitslip reorders the parallel data in the ISERDES block, allowing every combination of a
repeating serial pattern received by the deserializer to be presented to the FPGA fabric.
This repeating serial pattern is typically called a training pattern (training patterns are
supported by many networking and telecom standards).
By asserting the Bitslip pin of the ISERDES block, the incoming serial data stream is
reordered at the parallel side. This operation is repeated until the training pattern is seen.
The tables in
For illustrative purposes the data width is eight. The Bitslip operation is synchronous to
CLKDIV. In SDR mode, every Bitslip operation causes the output pattern to shift left by
one. In DDR mode, every Bitslip operation causes the output pattern to alternate between
a shift right by one and shift left by three. In this example, on the eighth Bitslip operation,
the output pattern reverts to the initial pattern. This assumes that serial data is an eight bit
repeating pattern.
X-Ref Target - Figure 8-10
Bitslip Operation in SDR Mode
Operations
Figure 8-10
Executed
Bitslip
Initial
1
2
3
4
5
6
7
Figure 8-10: Bitslip Operation Examples
illustrate the effects of a Bitslip operation in SDR and DDR mode.
www.xilinx.com
Pattern (8:1)
10010011
00100111
01001110
10011100
00111001
01110010
11100100
11001001
Output
Bitslip Operation in DDR Mode
Operations
Executed
Bitslip
Initial
1
2
3
4
5
6
7
Pattern (8:1)
00100111
10010011
10011100
01001110
01110010
00111001
11001001
11100100
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
ug190_8_10_100307
Output