XC5VLX50T-1FFG665C Xilinx Inc, XC5VLX50T-1FFG665C Datasheet - Page 369

• Manufacturer Part Number: XC5VLX50T-1FFG665C
• Description: FPGA, VIRTEX-5 LXT, 50K, 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG665C

• No. Of Logic Blocks: 7200
• Family Type: Virtex-5
• No. Of Speed Grades: 1
• Total Ram Bits: 2211840
• No. Of I/o's: 360
• Clock Management: DCM, PLL
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 550MHz
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 665-BBGA, FCBGA
• Core Supply Voltage Range: 1V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1565

Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
X-Ref Target - Figure 8-13
Clock Event 4
The first two bits of the fourth word CD have been sampled into the input side registers of
the ISERDES. On this same edge of CLKDIV, the second word sampled is presented to
Q1–Q4 with one bit shifted to the right. The actual bits from the input stream that appear
at the Q1–Q4 outputs during this cycle are shown in B of
The realigned bits on Q1–Q4 are sampled into the FPGA logic on the CLKDIV domain. The
total latency from when the ISERDES captures the asserted Bitslip input to when the
realigned ISERDES outputs Q1–Q4 are sampled by CLKDIV is two CLKDIV cycles.
Clock Event 5
The third word sampled is presented to Q1–Q4 with three bits shifted to the left. The actual
bits from the input stream that appear at the Q1–Q4 outputs during this cycle are shown in
C of
Figure
C
A
B
8-13.
Q1–Q4 During Clock Event 3
(No Bitslip)
Q1–Q4 During Clock Event 4
(1st Bitslip, Rotate 1 Bit to Right)
Q1–Q4 During Clock Event 5
(2nd Bitslip, Rotate 3 Bits to Left)
Figure 8-13: Bits from Data Input Stream (D) of
www.xilinx.com
Input Serial-to-Parallel Logic Resources (ISERDES)
C D A B C D
C D A B C D
C D A B C D
Figure
A B C D A B
A B C D A B
A B C D A B
8-13.
Figure 8-12
ug190_c8_13_100307
C D
C D
C D
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